RISC-V: Support Zilsd code gen

This commit adds the code gen support for Zilsd, which is a
newly added extension for RISC-V. The Zilsd extension allows
for loading and storing 64-bit values using even-odd register
pairs.

We only try to do miminal code gen support for that, which means only
use the new instructions when the load store is 64 bits data, we can use
that to optimize the code gen of memcpy/memset/memmove and also the
prologue and epilogue of functions, but I think that probably should be
done in a follow up patch.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_legitimize_move): Handle
	load/store with odd-even reg pair.
	(riscv_split_64bit_move_p): Don't split load/store if zilsd enabled.
	(riscv_hard_regno_mode_ok): Only allow even reg can be used for
	64 bits mode for zilsd.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zilsd-code-gen.c: New test.

0 files changed, 0 insertions, 0 deletions