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author | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-01-29 00:07:09 +0100 |
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committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-01-29 00:07:58 +0100 |
commit | 2f2101c87ac88a9fa9f7b4a264fb7738118c7fc9 (patch) | |
tree | 3d9150a4b8b07d4592b875e0fbffea094ce5dcb5 /libstdc++-v3 | |
parent | 38bce6ff4499597e4f9e2117deaa53362823f6e0 (diff) | |
download | gcc-2f2101c87ac88a9fa9f7b4a264fb7738118c7fc9.zip gcc-2f2101c87ac88a9fa9f7b4a264fb7738118c7fc9.tar.gz gcc-2f2101c87ac88a9fa9f7b4a264fb7738118c7fc9.tar.bz2 |
aarch64: Correct the maximum shift amount for shifted operands
The aarch64 ISA specification allows a left shift amount to be applied
after extension in the range of 0 to 4 (encoded in the imm3 field).
This is true for at least the following instructions:
* ADD (extend register)
* ADDS (extended register)
* SUB (extended register)
The result of this patch can be seen, when compiling the following code:
uint64_t myadd(uint64_t a, uint64_t b)
{
return a+(((uint8_t)b)<<4);
}
Without the patch the following sequence will be generated:
0000000000000000 <myadd>:
0: d37c1c21 ubfiz x1, x1, #4, #8
4: 8b000020 add x0, x1, x0
8: d65f03c0 ret
With the patch the ubfiz will be merged into the add instruction:
0000000000000000 <myadd>:
0: 8b211000 add x0, x0, w1, uxtb #4
4: d65f03c0 ret
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_uxt_size): fix an
off-by-one in checking the permissible shift-amount.
Diffstat (limited to 'libstdc++-v3')
0 files changed, 0 insertions, 0 deletions