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author | Jiawei <jiawei@iscas.ac.cn> | 2025-05-27 14:37:03 +0800 |
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committer | Jiawei <jiawei@iscas.ac.cn> | 2025-06-04 14:37:53 +0800 |
commit | f8251b4fce20f030fb133de1cadb06f95f01656e (patch) | |
tree | c425215edde18ce19be8250717b79a4a641d4b08 /libstdc++-v3/testsuite/std | |
parent | 102b21f9ce7d7a30cdee7c729a152e95c96107ac (diff) | |
download | gcc-f8251b4fce20f030fb133de1cadb06f95f01656e.zip gcc-f8251b4fce20f030fb133de1cadb06f95f01656e.tar.gz gcc-f8251b4fce20f030fb133de1cadb06f95f01656e.tar.bz2 |
RISC-V: Add Shlcofideleg extension.
This patch add the RISC-V Shlcofideleg extension. It supports delegating
LCOFI interrupts(the count-overflow interrupts) to VS-mode.[1]
[1] https://riscv.github.io/riscv-isa-manual/snapshot/privileged
gcc/ChangeLog:
* config/riscv/riscv-ext.def: New extension defs.
* config/riscv/riscv-ext.opt: Ditto.
* doc/riscv-ext.texi: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-shlocofideleg.c: New test.
Signed-off-by: Jiawei <jiawei@iscas.ac.cn>
Diffstat (limited to 'libstdc++-v3/testsuite/std')
0 files changed, 0 insertions, 0 deletions