[PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

Updated the test for rv32 accordingly and no regress found for runs like
"runtest --tool gcc --target_board='riscv-sim/-march=rv32gc_zba_zbb_zbc_zbs/-mabi=ilp32d/-mcmodel=medlow' riscv.exp" and
"runtest --tool gcc --target_board='riscv-sim/-march=rv64gc_zba_zbb_zbc_zbs/-mabi=lp64d/-mcmodel=medlow' riscv.exp"

lint warnings can be ignored for riscv-cores.def and riscv-ext-mips.def

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_CORE): Updated the supported march.
	* config/riscv/riscv-ext-mips.def (DEFINE_RISCV_EXT):
	New file added for mips conditional mov extension.
	* config/riscv/riscv-ext.def: Likewise.
	* config/riscv/t-riscv: Generates riscv-ext.opt
	* config/riscv/riscv-ext.opt: Generated file.
	* config/riscv/riscv.cc (riscv_expand_conditional_move): Updated for mips cmov
	and outlined some code that handle arch cond move.
	* config/riscv/riscv.md (mov<mode>cc): updated expand for MIPS CCMOV.
	* config/riscv/mips-insn.md: New file for mips-p8700 ccmov insn.
	* doc/riscv-ext.texi: Updated for mips cmov.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mipscondmov.c: Test file for mips.ccmov insn.

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