RISC-V: fix stack access before allocation.

In current riscv stack frame allocation, 2 steps are used. The first step allocates memories at least for callee saved GPRs and FPRs, and the second step allocates the rest if stack size is greater than signed 12-bit range. But it's observed in some cases, like gcc.target/riscv/stack_frame.c in my patch, callee saved FPRs fail to be included in the first step allocation, so we get generated instructions like this:

	li	t0,-16384
	addi	sp,sp,-48
	addi	t0,t0,752
	...
	fsw	fs4,-4(sp) #issue here of accessing before allocation
	...
	add	sp,sp,t0

"fsw	fs4,-4(sp)" has issue here of accessing stack before allocation. Although "add	sp,sp,t0" reserves later the memory for fs4, it exposes a risk when an interrupt comes in between "fsw	fs4,-4(sp)" and "add	sp,sp,t0", resulting in a corruption in the stack storing fs4 after interrupt context saving and a failure to get the correct value of fs4 later.

This patch fixes issue above, adapts testcases identified in regression tests, and add a new testcase for the change.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_first_stack_step): Fix computation
	of MIN_FIRST_STEP to cover FP save area too.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/pr93304.c: Adapt testcase for the change, constrain
	match to assembly instructions only.
	* gcc.target/riscv/rvv/base/spill-11.c: Adapt testcase for the change.
	* gcc.target/riscv/stack_frame.c: New test.

0 files changed, 0 insertions, 0 deletions