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| author | Andrew Waterman <andrew@sifive.com> | 2019-04-30 16:45:36 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2019-04-30 16:45:36 -0700 |
| commit | 4f4753914455ad186f7c1f994743abfcb05a7dc9 (patch) | |
| tree | ea27d5dc06f14353730b400aa7f7976d21608cf4 /libstdc++-v3/include/std/complex | |
| parent | 598f50d7891b420331f2027e60ba63824d335bad (diff) | |
| download | gcc-4f4753914455ad186f7c1f994743abfcb05a7dc9.zip gcc-4f4753914455ad186f7c1f994743abfcb05a7dc9.tar.gz gcc-4f4753914455ad186f7c1f994743abfcb05a7dc9.tar.bz2 | |
RISC-V: Short-forward-branch opt for SiFive 7 series cores.
gcc/
* config/riscv/constraints.md (L): New.
* config/riscv/predicates.md (lui_operand): New.
(sfb_alu_operand): New.
* config/riscv/riscv-protos.h (riscv_expand_conditional_move): Declare.
* config/riscv/riscv.c (riscv_expand_conditional_move): New.
* config/riscv/riscv.h (TARGET_SFB_ALU): New.
* config/riscv/risc.md (type): Add sfb_alu.
(branch<mode>): Renamed from branch_order<mode>. Change predicate for
operand 3 to reg_or_0_operand. In output string, change %3 to %z3.
(branch_zero<mode>): Delete.
(mov<mode>cc): New.
(mov<GPR:mode><X:mode>cc): Likewise.
* config/riscv/sifive-7.md (sifive_7_sfb_alu): New. Use in bypasses.
From-SVN: r270758
Diffstat (limited to 'libstdc++-v3/include/std/complex')
0 files changed, 0 insertions, 0 deletions