Add memory barriers to the double-checked locking used for static initialization.

libstdc++:
        Add memory barriers to the double-checked locking used for static
        initialization.
        * libsupc++/guard.cc (__test_and_acquire): Define default.
        (_GLIBCXX_GUARD_TEST_AND_ACQUIRE, __set_and_release)
        (_GLIBCXX_GUARD_SET_AND_RELEASE): Likewise.
        (recursion_push, recursion_pop): New abstraction functions.
        (__cxa_guard_acquire): Use _GLIBCXX_GUARD_TEST_AND_ACQUIRE.
        (__cxa_guard_release): Use _GLIBCXX_GUARD_SET_AND_RELEASE.
        * config/cpu/generic/cxxabi_tweaks.h (_GLIBCXX_GUARD_TEST): Rename
        from _GLIBCXX_GUARD_ACQUIRE and reverse sense.
        (_GLIBCXX_GUARD_SET): Rename from _GLIBCXX_GUARD_RELEASE.
        * config/cpu/arm/cxxabi_tweaks.h: Likewise.
        * config/cpu/alpha/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER)
        (_GLIBCXX_WRITE_MEM_BARRIER): Define.
        * config/cpu/powerpc/atomic_word.h: Likewise.
        * config/cpu/sparc/atomic_word.h: Likewise.
        * config/cpu/generic/atomic_word.h: Define them, commented out.
        * include/bits/atomicity.h: Define defaults.
        * config/cpu/ia64/atomic_word.h (__test_and_acquire)
        (__set_and_release): New inlines.
        (_GLIBCXX_GUARD_TEST_AND_ACQUIRE): Define.
        (_GLIBCXX_GUARD_SET_AND_RELEASE): Define.

        * libsupc++/guard.cc (acquire_1): Use __builtin_trap instead of
        abort();

gcc:
        * doc/tm.texi (TARGET_RELAXED_ORDERING): Document.
        * target.h (struct gcc_target): Add relaxed_ordering field.
        * target-def.h (TARGET_RELAXED_ORDERING): Define default.
        (TARGET_INITIALIZER): Add it.
        * config/alpha/alpha.c (TARGET_RELAXED_ORDERING): Define.
        * config/ia64/ia64.c (TARGET_RELAXED_ORDERING): Define.
        * config/rs6000/rs6000.c (TARGET_RELAXED_ORDERING): Define.
        * config/sparc/sparc.c (TARGET_RELAXED_ORDERING): Define.
        * cp/decl.c (expand_static_init): Don't use shortcut if
        targetm.relaxed_ordering.

From-SVN: r92659

7 files changed, 178 insertions, 6 deletions

diff --git a/libstdc++-v3/config/cpu/alpha/atomic_word.h b/libstdc++-v3/config/cpu/alpha/atomic_word.h
new file mode 100644
index 0000000..254e3d9
--- /dev/null
+++ b/libstdc++-v3/config/cpu/alpha/atomic_word.h
@@ -0,0 +1,38 @@
+// Low-level type for atomic operations -*- C++ -*-
+
+// Copyright (C) 2004 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 2, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING.  If not, write to the Free
+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
+// USA.
+
+// As a special exception, you may use this file as part of a free software
+// library without restriction.  Specifically, if other files instantiate
+// templates or use macros or inline functions from this file, or you compile
+// this file and link it with other files to produce an executable, this
+// file does not by itself cause the resulting executable to be covered by
+// the GNU General Public License.  This exception does not however
+// invalidate any other reasons why the executable file might be covered by
+// the GNU General Public License.
+
+#ifndef _GLIBCXX_ATOMIC_WORD_H
+#define _GLIBCXX_ATOMIC_WORD_H	1
+
+typedef int _Atomic_word;
+
+#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("mb":::"memory")
+#define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("wmb":::"memory")
+
+#endif 
diff --git a/libstdc++-v3/config/cpu/arm/cxxabi_tweaks.h b/libstdc++-v3/config/cpu/arm/cxxabi_tweaks.h
index 06c16fa..39a1043 100644
--- a/libstdc++-v3/config/cpu/arm/cxxabi_tweaks.h
+++ b/libstdc++-v3/config/cpu/arm/cxxabi_tweaks.h
@@ -38,8 +38,8 @@ namespace __cxxabiv1
 #ifdef __ARM_EABI__
   // The ARM EABI uses the least significant bit of a 32-bit
   // guard variable.  */
-#define _GLIBCXX_GUARD_ACQUIRE(x) (!(*(x) & 1))
-#define _GLIBCXX_GUARD_RELEASE(x) *(x) = 1
+#define _GLIBCXX_GUARD_TEST(x) ((*(x) & 1) != 0)
+#define _GLIBCXX_GUARD_SET(x) *(x) = 1
   typedef int __guard;
 
   // We also want the element size in array cookies.
@@ -54,8 +54,8 @@ namespace __cxxabiv1
 #else // __ARM_EABI__
 
   // The generic ABI uses the first byte of a 64-bit guard variable.
-#define _GLIBCXX_GUARD_ACQUIRE(x) (!*(char *) (x))
-#define _GLIBCXX_GUARD_RELEASE(x) *(char *) (x) = 1
+#define _GLIBCXX_GUARD_TEST(x) (*(char *) (x) != 0)
+#define _GLIBCXX_GUARD_SET(x) *(char *) (x) = 1
   __extension__ typedef int __guard __attribute__((mode (__DI__)));
 
   // __cxa_vec_ctor has void return type.
diff --git a/libstdc++-v3/config/cpu/generic/atomic_word.h b/libstdc++-v3/config/cpu/generic/atomic_word.h
index b46adc2..f03f1ec 100644
--- a/libstdc++-v3/config/cpu/generic/atomic_word.h
+++ b/libstdc++-v3/config/cpu/generic/atomic_word.h
@@ -32,4 +32,17 @@
 
 typedef int _Atomic_word;
 
+// Define these two macros using the appropriate memory barrier for the target.
+// The commented out versions below are the defaults.
+// See ia64/atomic_word.h for an alternative approach.
+
+// This one prevents loads from being hoisted across the barrier;
+// in other words, this is a Load-Load acquire barrier.
+// This is necessary iff TARGET_RELAXED_ORDERING is defined in tm.h.  
+// #define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("":::"memory")
+
+// This one prevents stores from being sunk across the barrier; in other
+// words, a Store-Store release barrier.
+// #define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
+
 #endif 
diff --git a/libstdc++-v3/config/cpu/generic/cxxabi_tweaks.h b/libstdc++-v3/config/cpu/generic/cxxabi_tweaks.h
index 5cacb3c..b5808a2 100644
--- a/libstdc++-v3/config/cpu/generic/cxxabi_tweaks.h
+++ b/libstdc++-v3/config/cpu/generic/cxxabi_tweaks.h
@@ -36,8 +36,8 @@ namespace __cxxabiv1
 #endif
 
   // The generic ABI uses the first byte of a 64-bit guard variable.
-#define _GLIBCXX_GUARD_ACQUIRE(x) (!*(char *) (x))
-#define _GLIBCXX_GUARD_RELEASE(x) *(char *) (x) = 1
+#define _GLIBCXX_GUARD_TEST(x) (*(char *) (x) != 0)
+#define _GLIBCXX_GUARD_SET(x) *(char *) (x) = 1
   __extension__ typedef int __guard __attribute__((mode (__DI__)));
 
   // __cxa_vec_ctor has void return type.
diff --git a/libstdc++-v3/config/cpu/ia64/atomic_word.h b/libstdc++-v3/config/cpu/ia64/atomic_word.h
new file mode 100644
index 0000000..2e49e27
--- /dev/null
+++ b/libstdc++-v3/config/cpu/ia64/atomic_word.h
@@ -0,0 +1,69 @@
+// Low-level type for atomic operations -*- C++ -*-
+
+// Copyright (C) 2004 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 2, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING.  If not, write to the Free
+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
+// USA.
+
+// As a special exception, you may use this file as part of a free software
+// library without restriction.  Specifically, if other files instantiate
+// templates or use macros or inline functions from this file, or you compile
+// this file and link it with other files to produce an executable, this
+// file does not by itself cause the resulting executable to be covered by
+// the GNU General Public License.  This exception does not however
+// invalidate any other reasons why the executable file might be covered by
+// the GNU General Public License.
+
+#ifndef _GLIBCXX_ATOMIC_WORD_H
+#define _GLIBCXX_ATOMIC_WORD_H	1
+
+#include <cxxabi.h>
+
+typedef int _Atomic_word;
+
+namespace __gnu_cxx
+{
+  // Test the first byte of __g and ensure that no loads are hoisted across
+  // the test.
+  inline bool
+  __test_and_acquire (__cxxabiv1::__guard *__g)
+  {
+    unsigned char __c;
+    unsigned char *__p = reinterpret_cast<unsigned char *>(__g);
+    // ldN.acq is a load with an implied hoist barrier.
+    // would ld8+mask be faster than just doing an ld1?
+    __asm __volatile ("ld1.acq %0 = %1" : "=r"(__c) : "m"(*__p) : "memory");
+    return __c != 0;
+  }
+
+  // Set the first byte of __g to 1 and ensure that no stores are sunk
+  // across the store.
+  inline void
+  __set_and_release (__cxxabiv1::__guard *__g)
+  {
+    unsigned char *__p = reinterpret_cast<unsigned char *>(__g);
+    // stN.rel is a store with an implied sink barrier.
+    // could load word, set flag, and CAS it back
+    __asm __volatile ("st1.rel %0 = %1" : "=m"(*__p) : "r"(1) : "memory");
+  }
+
+  // We don't define the _BARRIER macros on ia64 because the barriers are
+  // included in the test and set, above.
+#define _GLIBCXX_GUARD_TEST_AND_ACQUIRE(G) __gnu_cxx::__test_and_acquire (G)
+#define _GLIBCXX_GUARD_SET_AND_RELEASE(G) __gnu_cxx::__set_and_release (G)
+}
+
+#endif 
diff --git a/libstdc++-v3/config/cpu/powerpc/atomic_word.h b/libstdc++-v3/config/cpu/powerpc/atomic_word.h
new file mode 100644
index 0000000..ff418cc
--- /dev/null
+++ b/libstdc++-v3/config/cpu/powerpc/atomic_word.h
@@ -0,0 +1,38 @@
+// Low-level type for atomic operations -*- C++ -*-
+
+// Copyright (C) 2004 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library.  This library is free
+// software; you can redistribute it and/or modify it under the
+// terms of the GNU General Public License as published by the
+// Free Software Foundation; either version 2, or (at your option)
+// any later version.
+
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+
+// You should have received a copy of the GNU General Public License along
+// with this library; see the file COPYING.  If not, write to the Free
+// Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307,
+// USA.
+
+// As a special exception, you may use this file as part of a free software
+// library without restriction.  Specifically, if other files instantiate
+// templates or use macros or inline functions from this file, or you compile
+// this file and link it with other files to produce an executable, this
+// file does not by itself cause the resulting executable to be covered by
+// the GNU General Public License.  This exception does not however
+// invalidate any other reasons why the executable file might be covered by
+// the GNU General Public License.
+
+#ifndef _GLIBCXX_ATOMIC_WORD_H
+#define _GLIBCXX_ATOMIC_WORD_H	1
+
+typedef int _Atomic_word;
+
+#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("isync":::"memory")
+#define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
+
+#endif 
diff --git a/libstdc++-v3/config/cpu/sparc/atomic_word.h b/libstdc++-v3/config/cpu/sparc/atomic_word.h
index 941fddd..59b1a2c 100644
--- a/libstdc++-v3/config/cpu/sparc/atomic_word.h
+++ b/libstdc++-v3/config/cpu/sparc/atomic_word.h
@@ -36,4 +36,18 @@
   typedef int _Atomic_word;
 #endif
 
+#if defined(__sparc_v9__)
+// These are necessary under the V9 RMO model, though it is almost never
+// used in userspace.
+#define _GLIBCXX_READ_MEM_BARRIER \
+  __asm __volatile ("membar #LoadLoad":::"memory")
+#define _GLIBCXX_WRITE_MEM_BARRIER \
+  __asm __volatile ("membar #StoreStore":::"memory")
+
+#elif defined(__sparc_v8__)
+// This is necessary under the PSO model.
+#define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("stbar":::"memory")
+
+#endif
+
 #endif