diff options
| author | Alex Coplan <alex.coplan@arm.com> | 2021-05-10 09:46:45 +0100 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2021-05-10 09:46:45 +0100 |
| commit | 7596c762137f26f495b53ec93471273887832e31 (patch) | |
| tree | 4fe07feb8c8287c46c97ae5bc7f1a9e676956902 /libphobos/src | |
| parent | a2d7e58f4ea787eafdf3e7d39567739451d12d39 (diff) | |
| download | gcc-7596c762137f26f495b53ec93471273887832e31.zip gcc-7596c762137f26f495b53ec93471273887832e31.tar.gz gcc-7596c762137f26f495b53ec93471273887832e31.tar.bz2 | |
arm: Fix wrong code with MVE V2DImode loads and stores [PR99960]
As the PR shows, we currently miscompile V2DImode loads and stores for
MVE. We're currently using 64-bit loads/stores, but need to be using
128-bit vector loads and stores. Fixed thusly.
Some intrinsics tests were checking that we (incorrectly) used the
64-bit loads/stores: these have been updated.
gcc/ChangeLog:
PR target/99960
* config/arm/mve.md (*mve_mov<mode>): Simplify output code. Use
vldrw.u32 and vstrw.32 for V2D[IF]mode loads and stores.
gcc/testsuite/ChangeLog:
PR target/99960
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c:
Update now that we're (correctly) using full 128-bit vector
loads/stores.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_s64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vldrdq_gather_base_wb_z_u64.c:
Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_int.c: Likewise.
* gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c:
Likewise.
Diffstat (limited to 'libphobos/src')
0 files changed, 0 insertions, 0 deletions