RISC-V: Support VLS mode for vec_set

This patch would like to add the VLS support vec_set, both INT
and FP are included.

Give sample code as below:

typedef long long vl_t \
  __attribute__((vector_size(2 * sizeof (long long))));

vl_t init_vl (vl_t v, unsigned index, unsigned value)
{
  v[index] = value;

  return v;
}

Before this patch:
init_vl:
  addi     sp,sp,-16
  vsetivli zero,2,e64,m1,ta,ma
  vle64.v  v1,0(a1)
  vse64.v  v1,0(sp)
  slli     a4,a2,32
  srli     a2,a4,29
  add      a2,sp,a2
  slli     a3,a3,32
  srli     a3,a3,32
  sd       a3,0(a2)
  vle64.v  v1,0(sp)
  vse64.v  v1,0(a0)
  addi     sp,sp,16
  jr       ra

After this patch:
init_vl:
  vsetivli    zero,2,e64,m1,ta,ma
  vle64.v     v1,0(a1)
  slli        a3,a3,32
  srli        a3,a3,32
  addi        a5,a2,1
  vsetvli     zero,a5,e64,m1,tu,ma
  vmv.v.x     v2,a3
  vslideup.vx v1,v2,a2
  vsetivli    zero,2,e64,m1,ta,ma
  vse64.v     v1,0(a0)
  ret

Please note this patch depends the RVV SCALAR_MOVE_MERGED_OP bugfix.

gcc/ChangeLog:

	* config/riscv/autovec.md: Extend to vls mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: New macros.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-10.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-11.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-12.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-13.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-14.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-15.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-16.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-17.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-18.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-19.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-20.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-21.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-22.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-5.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-6.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-7.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-8.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/vec-set-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions