LoongArch: Don't emit overly-restrictive barrier for LL-SC loops

For LL-SC loops, if the atomic operation has succeeded, the SC
instruction always imply a full barrier, so the barrier we manually
inserted only needs to take the account for the failure memorder, not
the success memorder (the barrier is skipped with "b 3f" on success
anyway).

Note that if we use the AMCAS instructions, we indeed need to consider
both the success memorder an the failure memorder deciding if "_db"
suffix is needed.  Thus the semantics of atomic_cas_value_strong<mode>
and atomic_cas_value_strong<mode>_amcas start to be different.  To
prevent the compiler from being too clever, use a different unspec code
for AMCAS instructions.

gcc/ChangeLog:

	* config/loongarch/sync.md (UNSPEC_COMPARE_AND_SWAP_AMCAS): New
	UNSPEC code.
	(atomic_cas_value_strong<mode>): NFC, update the comment to note
	we only need to consider failure memory order.
	(atomic_cas_value_strong<mode>_amcas): Use
	UNSPEC_COMPARE_AND_SWAP_AMCAS instead of
	UNSPEC_COMPARE_AND_SWAP.
	(atomic_compare_and_swap<mode:GPR>): Pass failure memorder to
	gen_atomic_cas_value_strong<mode>.
	(atomic_compare_and_swap<mode:SHORT>): Pass failure memorder to
	gen_atomic_cas_value_cmp_and_7_si.

0 files changed, 0 insertions, 0 deletions