s390.md: Replace TARGET_64BIT with TARGET_ZARCH.

2010-04-13  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
            Ulrich Weigand  <Ulrich.Weigand@de.ibm.com>
	
	* gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH.
	* gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with
	UNITS_PER_LONG where it is ABI relevant.	
	(s390_return_addr_rtx): Likewise.
	(s390_back_chain_rtx): Likewise.
	(s390_frame_area): Likewise.
	(s390_frame_info): Likewise.
	(s390_initial_elimination_offset): Likewise.
	(save_gprs): Likewise.
	(s390_emit_prologue): Likewise.
	(s390_emit_epilogue): Likewise.
	(s390_function_arg_advance): Likewise.
	(s390_function_arg): Likewise.
	(s390_va_start): Likewise.
	(s390_gimplify_va_arg): Likewise.
	(s390_function_profiler): Likewise.
	(s390_optimize_prologue): Likewise.
	(s390_rtx_costs): Likewise.
	(s390_secondary_reload): Likewise.
	(s390_promote_function_mode): Likewise.
	(s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH.
	(s390_scalar_mode_supported_p): Disallow TImode if no 64 bit
	registers available.
	(s390_unwind_word_mode): New function.
	(s390_function_value): Split 64 bit values into register pair if
	used as return value.
	(s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for
	function call parameters.  Handle parallels.
	(TARGET_SCALAR_MODE_SUPPORTED_P): New macro.
	(HARD_REGNO_CALL_PART_CLOBBERED): New macro.
	(DWARF_CIE_DATA_ALIGNMENT): New macro.
	(s390_expand_setmem): Remove unused variable src_addr.
	* gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to
	deal with 64 bit registers.	
	* gcc/config/s390/s390.h: Define __zarch__ predefined macro.
	Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant.
	(UNITS_PER_LONG): New macro.
	* libjava/include/s390-signal.h: Define extended ucontext
	structure containing the upper halfs of the 64 bit registers.


Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com>

From-SVN: r158257

1 files changed, 71 insertions, 3 deletions

diff --git a/libjava/include/s390-signal.h b/libjava/include/s390-signal.h
index fe965bd..4b0a61e 100644
--- a/libjava/include/s390-signal.h
+++ b/libjava/include/s390-signal.h
@@ -39,6 +39,7 @@ static void _name (int, siginfo_t *_si __attribute__((unused)), \
    and if dividend and divisor are as above, we simply return from the signal
    handler.  This causes execution to continue after the instruction.  
    Before returning, we the set result registers as expected.  */
+#define UC_EXTENDED	0x00000001
 
 #define HANDLE_DIVIDE_OVERFLOW						\
 do									\
@@ -47,6 +48,15 @@ do									\
     __builtin_extract_return_addr (_si->si_addr);			\
   unsigned long *_regs = _uc->uc_mcontext.gregs;			\
   int _r1, _r2, _d2, _x2, _b2;						\
+  struct                                                                \
+  {                                                                     \
+    unsigned long int uc_flags;                                         \
+    struct ucontext *uc_link;                                           \
+    stack_t uc_stack;                                                   \
+    mcontext_t uc_mcontext;                                             \
+    unsigned long sigmask[2];                                           \
+    unsigned long ext_regs[16];						\
+  } *_uc_ext = (typeof(_uc_ext))_uc;					\
 									\
   /* First, a couple of helper routines to decode instructions.  */	\
   struct _decode 							\
@@ -119,8 +129,16 @@ do									\
       {									\
 	return _d + (_x? _regs[_x] : 0) + (_b? _regs[_b] : 0);		\
       }									\
-    };									\
 									\
+      static inline int is_long_long_min_p (unsigned long *_regs,       \
+					    unsigned long *_ext_regs,   \
+					    int _r)			\
+      {									\
+	return ((long long)_regs[_r]					\
+		| (long long)_ext_regs[_r] << 32) ==			\
+	  LONG_LONG_MIN;						\
+      }									\
+  };									\
 									\
   /* DR r1,r2 */							\
   if (_decode::_is_rr (_eip, 0x1d, &_r1, &_r2)				\
@@ -175,8 +193,58 @@ do									\
       _regs[_r1] = 0;							\
       return;								\
     }									\
-									\
-}									\
+                                                                        \
+  /* The extended ucontext contains the upper halfs of the 64bit	\
+     registers in 31bit applications.  */				\
+  if (_uc->uc_flags & 1 == 1)						\
+    {             							\
+      /* DSGR r1,r2 */							\
+      if (_decode::_is_rre (_eip, 0xb9, 0x0d, &_r1, &_r2)		\
+	  && (int) _regs[_r2] == -1					\
+	  && (int) _uc_ext->ext_regs[_r2] == -1				\
+	  && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs,	\
+					  _r1 + 1))			\
+	{								\
+	  _regs[_r1] = 0;						\
+	  _uc_ext->ext_regs[_r1] = 0;					\
+	  return;							\
+	}								\
+      									\
+      /* DSGFR r1,r2 */							\
+      if (_decode::_is_rre (_eip, 0xb9, 0x1d, &_r1, &_r2)		\
+	  && (int) _regs[_r2] == -1					\
+	  && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs,	\
+					  _r1 + 1))			\
+	{								\
+	  _regs[_r1] = 0;						\
+	  _uc_ext->ext_regs[_r1] = 0;					\
+	  return;							\
+	}								\
+      									\
+      /* DSG r1,d2(x2,b2) */						\
+      if (_decode::_is_rxy (_eip, 0xe3, 0x0d, &_r1, &_d2, &_x2, &_b2)	\
+	  && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1	\
+	  && *(int *) _decode::_eff (_regs, _d2 + 4, _x2, _b2) == -1	\
+	  && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs,	\
+					  _r1 + 1))			\
+	{								\
+	  _regs[_r1] = 0;						\
+	  _uc_ext->ext_regs[_r1] = 0;					\
+	  return;							\
+	}								\
+	      								\
+      /* DSGF r1,d2(x2,b2) */						\
+      if (_decode::_is_rxy (_eip, 0xe3, 0x1d, &_r1, &_d2, &_x2, &_b2)	\
+	  && *(int *) _decode::_eff (_regs, _d2, _x2, _b2) == -1	\
+	  && _decode::is_long_long_min_p (_regs, _uc_ext->ext_regs,	\
+					  _r1 + 1))			\
+	{								\
+	  _regs[_r1] = 0;						\
+	  _uc_ext->ext_regs[_r1] = 0;					\
+	  return;							\
+	}								\
+    }									\
+ }                                                                      \
 while (0)
 
 /* For an explanation why we cannot simply use sigaction to