aboutsummaryrefslogtreecommitdiff
path: root/libjava
diff options
context:
space:
mode:
authorAlexey Merzlyakov <alexey.merzlyakov@samsung.com>2025-04-18 06:45:10 -0600
committerJeff Law <jlaw@ventanamicro.com>2025-04-18 06:46:03 -0600
commit529a43109fcd93f5aafda345da14679f538ada86 (patch)
tree1990845bd18fd94a32d0bada51122eae0672c1e9 /libjava
parent6808f74b4f07decb3727624f0e62e7c57ae87022 (diff)
downloadgcc-529a43109fcd93f5aafda345da14679f538ada86.zip
gcc-529a43109fcd93f5aafda345da14679f538ada86.tar.gz
gcc-529a43109fcd93f5aafda345da14679f538ada86.tar.bz2
[PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016]
It fixes one of the PR108016 mis-optimization. The patch adjusts expanding for __builtin_add/sub_overflow() on RV64 targets to avoid unnecessary sext.w instructions. It replaces expanded for ADD/SUB_OVERFLOW code: r141:SI=r139:DI#0+r140:DI#0 .. r143:DI=sign_extend(r141:SI) to the followong kind of chain -> r143:DI=sign_extend(r139:DI#0+r140:DI#0) .. r141:SI=r143:DI#0 so that sign_extend(a:SI+b:SI) to be emitted as addw (or subw) instruction, while output r141:SI register will be placed at the end of chain without extra dependencies, and thus could be easily optimized-out by further pipeline. PR middle-end/108016 gcc/ChangeLog: * config/riscv/riscv.md (addv<mode>4, uaddv<mode>4, subv<mode>4, usubv<mode>4): Tunes for unnecessary sext.w elimination. PR middle-end/108016 gcc/testsuite/ChangeLog: * gcc.target/riscv/pr108016.c: New test.
Diffstat (limited to 'libjava')
0 files changed, 0 insertions, 0 deletions