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| author | Mike Stump <mrs@apple.com> | 2006-11-28 06:05:25 +0000 |
|---|---|---|
| committer | Mike Stump <mrs@gcc.gnu.org> | 2006-11-28 06:05:25 +0000 |
| commit | 69a498424152c5d13d5fa8a4cca4176f27ceceb5 (patch) | |
| tree | fff2aca16cb8eb6c9d57fee5555601236821ecbb /libjava/sysdep/x86-64 | |
| parent | 7523cace86c3739099763b969614c5cd3eee4994 (diff) | |
| download | gcc-69a498424152c5d13d5fa8a4cca4176f27ceceb5.zip gcc-69a498424152c5d13d5fa8a4cca4176f27ceceb5.tar.gz gcc-69a498424152c5d13d5fa8a4cca4176f27ceceb5.tar.bz2 | |
locks.h: Enable use of either file on either target to support multilibs from one to the...
* sysdep/x86-64/locks.h: Enable use of either file on either
target to support multilibs from one to the other.
* sysdep/i386/locks.h: Likewise.
From-SVN: r119276
Diffstat (limited to 'libjava/sysdep/x86-64')
| -rw-r--r-- | libjava/sysdep/x86-64/locks.h | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/libjava/sysdep/x86-64/locks.h b/libjava/sysdep/x86-64/locks.h index 7fb9bbb..fdc0a3e 100644 --- a/libjava/sysdep/x86-64/locks.h +++ b/libjava/sysdep/x86-64/locks.h @@ -1,4 +1,4 @@ -/* locks.h - Thread synchronization primitives. x86-64 implementation. +/* locks.h - Thread synchronization primitives. X86/x86-64 implementation. Copyright (C) 2002 Free Software Foundation @@ -21,7 +21,9 @@ typedef size_t obj_addr_t; /* Integer type big enough for object */ // Assumed to have acquire semantics, i.e. later memory operations // cannot execute before the compare_and_swap finishes. inline static bool -compare_and_swap(volatile obj_addr_t *addr, obj_addr_t old, obj_addr_t new_val) +compare_and_swap(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) { char result; #ifdef __x86_64__ @@ -31,7 +33,7 @@ compare_and_swap(volatile obj_addr_t *addr, obj_addr_t old, obj_addr_t new_val) : "memory"); #else __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1" - : "=m"(*(addr)), "=q"(result) + : "=m"(*addr), "=q"(result) : "r" (new_val), "a"(old), "m"(*addr) : "memory"); #endif @@ -41,7 +43,7 @@ compare_and_swap(volatile obj_addr_t *addr, obj_addr_t old, obj_addr_t new_val) // Set *addr to new_val with release semantics, i.e. making sure // that prior loads and stores complete before this // assignment. -// On x86-64, the hardware shouldn't reorder reads and writes, +// On X86/x86-64, the hardware shouldn't reorder reads and writes, // so we just have to convince gcc not to do it either. inline static void release_set(volatile obj_addr_t *addr, obj_addr_t new_val) @@ -63,7 +65,7 @@ compare_and_swap_release(volatile obj_addr_t *addr, // Ensure that subsequent instructions do not execute on stale // data that was loaded from memory before the barrier. -// On x86-64, the hardware ensures that reads are properly ordered. +// On X86/x86-64, the hardware ensures that reads are properly ordered. inline static void read_barrier() { @@ -74,8 +76,8 @@ read_barrier() inline static void write_barrier() { - /* x86-64 does not reorder writes. We just need to ensure that gcc also - doesn't. */ + /* x86-64/X86 does not reorder writes. We just need to ensure that + gcc also doesn't. */ __asm__ __volatile__(" " : : : "memory"); } #endif |