RISC-V: Combine vsext.vf2 and vsll.vi to vwsll.vi on ZVBB

The vwsll.vi of zvbb ext take zero extend before ashift.  But
we can still do some combine based on sign extend if and only
if the shift is imm and the sign extend bits are all shifted.
For example as below

  vsetvli   zero, zero, e32, m1, ta, ma
  vsext.vf2 v1, v2
  vsll.vi   v1, v1, 16

If the ashift bits is greater than or equals to truncated bitsize,
(aka 16 for e32), the sign or zero extend bits will be ashifted
and never pollute the final result.  Then we have

  vsetvli   zero, zero, e32, m1, ta, ma
  vwsll.vi  v1, v2, 16

	PR target.121959

The below test suites are passed for this patch series.
 * The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*vwsll_sign_extend_<mode>): Add
	pattern to combine vsext.vf2 and vslli.vi to vwsll.vi.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr121959-1.c: New test.
	* gcc.target/riscv/rvv/autovec/pr121959-2.c: New test.
	* gcc.target/riscv/rvv/autovec/pr121959-3.c: New test.
	* gcc.target/riscv/rvv/autovec/pr121959-4.c: New test.
	* gcc.target/riscv/rvv/autovec/pr121959-5.c: New test.
	* gcc.target/riscv/rvv/autovec/pr121959-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/pr121959.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions