RISC-V: Add support for the XAndesvsintload ISA extension.

This extension defines vector load instructions to move sign-extended or
zero-extended INT4 data into 8-bit vector register elements.

gcc/ChangeLog:

	* config/riscv/andes-vector-builtins-bases.cc
	(nds_nibbleload): New class.
	* config/riscv/andes-vector-builtins-bases.h (nds_vln8): New def.
	(nds_vlnu8): Ditto.
	* config/riscv/andes-vector-builtins-functions.def (nds_vln8): Ditto.
	(nds_vlnu8): Ditto.
	* config/riscv/andes-vector.md (@pred_intload_mov<su><mode>): New pattern.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_Q_OPS): New def.
	(DEF_RVV_QU_OPS): Ditto.
	* config/riscv/riscv-vector-builtins.cc
	(q_v_void_const_ptr_ops): New operand information.
	(qu_v_void_const_ptr_ops): Ditto.
	* config/riscv/riscv-vector-builtins.def (void_const_ptr): New def.
	* config/riscv/riscv-vector-builtins.h (enum required_ext): Ditto.
	(required_ext_to_isa_name): Add case XANDESVSINTLOAD_EXT.
	(required_extensions_specified): Ditto.
	* config/riscv/vector-iterators.md (NDS_QVI): New iterator.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vln8.c: New test.
	* gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vln8.c: New test.
	* gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vln8.c: New test.
	* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vln8.c: New test.

0 files changed, 0 insertions, 0 deletions