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| author | Kito Cheng <kito.cheng@sifive.com> | 2025-05-12 14:36:07 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2025-05-19 11:37:33 +0800 |
| commit | c9eb473fb9946f642506d24f4131d7c83855fd78 (patch) | |
| tree | 528dcd147ba974577d37fc25f37b2e0c1e976407 /libjava/gnu/java/net/protocol/http | |
| parent | 3fc902e738bbf3f4b842ae0faa9313c7aee49e98 (diff) | |
| download | gcc-master.zip gcc-master.tar.gz gcc-master.tar.bz2 | |
This commit introduces a new operand constraint `cR` for the RISC-V
architecture, which allows the use of an even-odd RVC general purpose register
(x8-x15) in inline asm.
Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102
gcc/ChangeLog:
* config/riscv/constraints.md (cR): New constraint.
* doc/md.texi (Machine Constraints::RISC-V): Document the new cR
constraint.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/constraint-cR-pair.c: New test case.
Diffstat (limited to 'libjava/gnu/java/net/protocol/http')
0 files changed, 0 insertions, 0 deletions