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| author | Pan Li <pan2.li@intel.com> | 2025-04-28 20:35:10 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2025-05-13 07:07:34 +0800 |
| commit | c273a1c1846207082b60fe10c18f5c86dbcfd413 (patch) | |
| tree | 85dd4cece4385b1c4cfd318a91491b361ed99613 /libjava/classpath/vm/reference/java | |
| parent | f6535d433e250421f6c1f2f691c04e613d63a694 (diff) | |
| download | gcc-c273a1c1846207082b60fe10c18f5c86dbcfd413.zip gcc-c273a1c1846207082b60fe10c18f5c86dbcfd413.tar.gz gcc-c273a1c1846207082b60fe10c18f5c86dbcfd413.tar.bz2 | |
RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7
This patch will add testcase for unsigned integer SAT_ADD form 7:
#define DEF_VEC_SAT_U_ADD_FMT_9(WT, T) \
void __attribute__((noinline)) \
vec_sat_u_add_##WT##_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
T max = -1; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
WT val = (WT)x + (WT)y; \
out[i] = val > max ? max : (T)val; \
} \
}
DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint32_t)
The below test are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add test helper macros.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'libjava/classpath/vm/reference/java')
0 files changed, 0 insertions, 0 deletions