RISC-V: Add support for the XAndesvpackfph ISA extension.

This extension defines vector instructions to extract a pair of FP16 data from
a floating-point register. Multiply the top FP16 data with the FP16 elements
and add the result with the bottom FP16 data.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc:
	Turn on VECTOR_ELEN_FP_16 for XAndesvpackfph.
	* config/riscv/andes-vector-builtins-bases.cc (nds_vfpmad): New class.
	* config/riscv/andes-vector-builtins-bases.h: New def.
	* config/riscv/andes-vector-builtins-functions.def (nds_vfpmadt): Ditto.
	(nds_vfpmadb): Ditto.
	(nds_vfpmadt_frm): Ditto.
	(nds_vfpmadb_frm): Ditto.
	* config/riscv/andes-vector.md (@pred_nds_vfpmad<nds_tb><mode>):
	New pattern.
	* config/riscv/riscv-vector-builtins-types.def
	(DEF_RVV_F16_OPS): New def.
	* config/riscv/riscv-vector-builtins.cc (f16_ops): Ditto
	* config/riscv/riscv-vector-builtins.def (float32_type_node): Ditto.
	* config/riscv/riscv-vector-builtins.h (XANDESVPACKFPH_EXT): Ditto.
	(required_ext_to_isa_name): Add case XANDESVPACKFPH_EXT.
	(required_extensions_specified): Ditto.
	* config/riscv/vector-iterators.md (VHF): New iterator.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadb.c: New test.
	* gcc.target/riscv/rvv/xandesvector/non-policy/non-overloaded/nds_vfpmadt.c: New test.
	* gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadb.c: New test.
	* gcc.target/riscv/rvv/xandesvector/non-policy/overloaded/nds_vfpmadt.c: New test.
	* gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadb.c: New test.
	* gcc.target/riscv/rvv/xandesvector/policy/non-overloaded/nds_vfpmadt.c: New test.
	* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadb.c: New test.
	* gcc.target/riscv/rvv/xandesvector/policy/overloaded/nds_vfpmadt.c: New test.

0 files changed, 0 insertions, 0 deletions