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| author | Xi Ruoyao <xry111@xry111.site> | 2025-03-01 11:46:54 +0800 |
|---|---|---|
| committer | Lulu Cheng <chenglulu@loongson.cn> | 2025-08-18 09:09:37 +0800 |
| commit | 2aca41ba9769194bc740683616b7a539019993a7 (patch) | |
| tree | 89f1d486a577b5ee62fe6348473b5382b25cf624 /libjava/classpath/lib | |
| parent | 0f3c1b71daaa3f6cfc566347535a6a56662f2454 (diff) | |
| download | gcc-2aca41ba9769194bc740683616b7a539019993a7.zip gcc-2aca41ba9769194bc740683616b7a539019993a7.tar.gz gcc-2aca41ba9769194bc740683616b7a539019993a7.tar.bz2 | |
LoongArch: Implement 16-byte atomic store with sc.q
When LSX is not available but sc.q is (for example on LA664 where the
SIMD unit is not enabled), we can use a LL-SC loop for 16-byte atomic
store.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
Accept "%t" for printing the number of the 64-bit machine
register holding the upper half of a TImode.
* config/loongarch/sync.md (atomic_storeti_scq): New
define_insn.
(atomic_storeti): expand to atomic_storeti_scq if !ISA_HAS_LSX.
Diffstat (limited to 'libjava/classpath/lib')
0 files changed, 0 insertions, 0 deletions