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authorKonstantinos Eleftheriou <konstantinos.eleftheriou@vrull.eu>2025-05-19 13:00:05 +0200
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>2025-05-27 15:16:26 +0200
commitec5349c37afe972ee79b777ee749630b1a0a007e (patch)
tree0cf362170142256b65f91218eb2ab39b8f54abdf /libjava/classpath/lib/java
parent764ea9ea3ea0aab10b935ae5cd079d1d236b6bb9 (diff)
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asf: Fix calling of emit_move_insn on registers of different modes [PR119884]
This patch uses `lowpart_subreg` for the base register initialization, instead of zero-extending it. We had tried this solution before, but we were leaving undefined bytes in the upper part of the register. This shouldn't be happening as we are supposed to write the whole register when the load is eliminated. This was occurring when having multiple stores with the same offset as the load, generating a register move for all of them, overwriting the bit inserts that were inserted before them. In order to overcome this, we are removing redundant stores from the sequence, i.e. stores that write to addresses that will be overwritten by stores that come after them in the sequence. We are using the same bitmap that is used for the load elimination check, to keep track of the bytes that are written by each store. Also, we are now allowing the load to be eliminated even when there are overlaps between the stores, as there is no obvious reason why we shouldn't do that, we just want the stores to cover all of the load's bytes. Bootstrapped/regtested on AArch64 and x86_64. PR rtl-optimization/119884 gcc/ChangeLog: * avoid-store-forwarding.cc (process_store_forwarding): Use `lowpart_subreg` for the base register initialization and remove redundant stores from the store/load sequence. gcc/testsuite/ChangeLog: * gcc.target/i386/pr119884.c: New test.
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