[RISC-V] Add andi+bclr synthesis

So this patch from Shreya adds the ability to use andi + a series of bclr insns
to synthesize a logical AND, much like we're doing for IOR/XOR using ori+bset
or their xor equivalents.

This would regress from a code quality standpoint if we didn't make some
adjustments to a handful of define_insn_and_split patterns in the riscv backend
which support the same kind of idioms.

Essentially we turn those define_insn_and_split patterns into the simple
define_splits they always should have been.  That's been the plan since we
started down this path -- now is the time to make that change for a subset of
patterns.  It may be the case that when we're finished we may not even need
those patterns.  That's still TBD.

I'm aware of one minor regression in xalan.  As seen elsewhere, combine
reconstructs the mask value, uses mvconst_internal to load it into a reg then
an and instruction.  That looks better than the operation synthesis, but only
because of the mvconst_internal little white lie.

This patch does help in a variety of places.  It's fairly common in gimple.c
from 502.gcc to see cases where we'd use bclr to clear a bit, then set the
exact same bit a few instructions later.  That was an artifact of using a
define_insn_and_split -- it wasn't obvious to combine that we had two
instructions manipulating the same bit.  Now that is obvious to combine and the
redundant operation gets removed.

This has spun in my tester with no regressions on riscv32-elf and riscv64-elf.
Hopefully the baseline for the tester as stepped forward 🙂

gcc/
	* config/riscv/bitmanip.md (andi+bclr splits): Simplified from
	prior define_insn_and_splits.
	* config/riscv/riscv.cc (synthesize_and): Add support for andi+bclr
	sequences.

	    Co-authored-by: Jeff Law  <jlaw@ventanamicro.com>

0 files changed, 0 insertions, 0 deletions