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authorRichard Sandiford <rdsandiford@googlemail.com>2011-09-14 21:17:43 +0000
committerRichard Sandiford <rsandifo@gcc.gnu.org>2011-09-14 21:17:43 +0000
commit68ed2b9cb99a67587d4be07205fc644befe8cac1 (patch)
tree507bb55003cb2b2ee87ec894e3273abfb78dc5b8 /libjava/classpath/lib/java/util/IdentityHashMap$3.class
parentd7f99b2cc5dc6fe3269fb3bc5b872c9cc9cdbbd3 (diff)
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sh.md: Use match_test rather than eq/ne symbol_ref throughout file.
gcc/ * config/sh/sh.md: Use match_test rather than eq/ne symbol_ref throughout file. From-SVN: r178868
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2025-06-13x86: don't constrain %axl/%cxlJan Beulich2-4/+4
They can be used like their %al/%cl counterparts everywhere else; there's no apparent reason why they shouldn't be usable as accumulator / shift count respectively. Enforcing such a restriction only makes writing heavily macro-ized code more cumbersome.
2025-06-13x86: swap operands in OUT-with-immediate templateJan Beulich2-3/+5
In a number of places we assume that immediates come first in the set of operands. It is mere luck that so far OUT, having operands the other way around, wasn't negatively impacted by this. Leverage this to have a few loops start from the first non-immediate operand (or in one case to stop there). Note, however, that process_immext() inserts an immediate last, so especially all output_*() functions cannot be changed in the same way.
2025-06-13x86: refine UD<n> kind-of-insnsJan Beulich2-279/+306
While documentation of these continues to be lacking sufficient detail, it is becoming increasingly clear that in 66f1eba0b7e8 ("x86: correct UDn") I went too far with requiring operands, to populate a ModR/M byte. AMD hardware appears to always behave as indicated as "may" in PM 3.36, which for all practical purposes means there's no ModR/M byte. The SDM (rev 087) indicates that such behavior can occur on older hardware for UD0. Re-add an operand-less UD1 form (as well as its UD2B alias), while newly adding such a form also for UD0. Because of the ambiguity, there's no good/easy way of handling both possibilities in the disassembler, which hence remains unaltered. Further, from all information I'm able to gather, the 0F opcode space was only introduced with the i286; bump the minimal hardware requirement for all UD<n> accordingly.
2025-06-12aarch64: Add support for FEAT_FPRCVTRichard Ball7-3412/+3599
FEAT_FPRCVT introduces new versions of previous instructions. The instructions are used to convert between floating points and Integers. These new versions take as operands SIMD&FP registers for both the source and destination register. FEAT_FPRCVT also enables the use of some existing AdvSIMD instructions in streaming mode. However, no changes are needed in gas to support this.
2025-06-11aarch64: Add system registers for 2024 MPAM extensionYury Khrustalev1-0/+8
This patch adds support for new system registers introduced in the 2024 MPAM extension (Memory Partitioning and Monitoring): Available in Armv9.3-A: MPAMBW0_EL1, MPAMBW1_EL1, MPAMBW1_EL12, MPAMBW2_EL2, MPAMBW3_EL3, MPAMBWCAP_EL2, MPAMBWIDR_EL1 Available in Armv9.3-A with SME: MPAMBWSM_EL1 The details can be found in [1]. [1]: https://developer.arm.com/documentation/ddi0601/latest
2025-06-09aarch64: Fix typos in opcode headersYury Khrustalev1-2/+2
2025-06-04aarch64: Support id_aa64fpfr0_el1, id_aa64pfr2_el1Dmitry Chestnykh1-0/+2
2025-05-16x86: improve matching diagnostics when %st is involvedJan Beulich5-7422/+7424
Diagnosing operand size vs operand type mismatches doesn't work very well when GPRs and FPRs are in the same register class, distinguished just by size. Introduce a separate RegFP class.
2025-05-16RISC-V: Add zilsd & zclsd supportdysun1-0/+53
Ref: https://github.com/riscv/riscv-zilsd/blob/main/zilsd.adoc Signed-off-by: dysun <sundongya@nucleisys.com> Co-developed-by: LIU Xu <liuxu@nucleisys.com> Co-developed-by: ZHAO Fujin <zhaofujin@nucleisys.com>
2025-05-13aarch64: Replace incorrect commentAlice Carlotti1-7/+7
The comment explaining the placement of the cfinv entry before the generic msr entry in the opcode table was incorrect. The issue is unrelated to the all ones bitmask for cfinv, and is actually due the large number of architectural aliases of the msr instruction.
2025-05-12aarch64: Support for FEAT_RME_GPC3Ezra Sitorus1-0/+1
FEAT_RME_GPC3 - RME Granule Protection Check 3 Extension - introduces a method for defining a set of windows in the memory map for which Granule Protection Checks are skipped, and instead applies a set of default settings associated with the window. This patch introduces the sysreg gpcbw_el3. Add -march=armv9.5-a to access this sysreg since this feature is optional from armv9.5-a.
2025-05-12aarch64: Support for FEAT_OCCMOEzra Sitorus1-0/+4
FEAT_OCCMO - Outer Cacheable Cache Maintenance Operation - introduces system instructions that provides software with a mechanism to publish writes to the Outer cache level.
2025-05-09aarch64: Mark predicate-as-counter pseudo instructionsAlice Carlotti3-17/+33
Using explicit pseudo aliases is clearer and more consistent with other instruction aliases. This does not change behaviour. For the non-alias instructions (everything except mov) we already picked the first matching entry for disassembly by default. For mov we picked the last matching aliased entry, which remained the original alias since do_misc_decoding doesn't recognise OP_MOV_PN_PN.
2025-05-09aarch64: Mark clearbhb as a pseudo instructionAlice Carlotti1-1/+1
This was an early name for the clrbhb hint instruction. Some software was written with the old name before it was renamed, so we support it for assembly but should never use it in disassembly. This patch has no functional change, because we already pick (by default) the last matching alias in the opcode table, and clrbhb is listed later than clearbhb.
2025-05-09aarch64: Fix dgh disassemblyAlice Carlotti3-4/+5
2025-05-09aarch64: Mark SME mova aliasesAlice Carlotti3-60/+100
This will only change behaviour during disassembly with -M no-aliases.
2025-05-09aarch64: Mark rev64 as a pseudo instructionAlice Carlotti3-5/+5
This is more natural than raising the priority of rev with F_P1, and is functionally equivalent.
2025-05-09aarch64: Eliminate AARCH64_OPND_SVE_ADDR_RAlice Carlotti5-2304/+2252
Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept implicit XZR offsets. Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands to support instructions where an XZR offset is allowed but must be specified explicitly. This allows the removal of the duplicate opcode table entries using AARCH64_OPND_SVE_ADDR_R.
2025-05-09RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslspChao-ying Fu2-0/+48
Spec: https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp with verison 1.0. Passed binutils testsuites of targets elf32/elf64/linux32/linux64. Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
2025-05-07s390: Fix format specifier for VR in disassemblerJens Remus1-1/+1
Vector register (VR) numbers are unsigned. Use format specifier %u instead of %i. Reported-by: Florian Krohm <flo2030@eich-krohm.de> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-04-30RISC-V: Mark fgt.*/fge.* as instruction aliasKito Cheng1-8/+8
They are instruction alias, but not mark correctly, and seems like we don't have a good way to verify that since the disassembler doesn't disassemble instruction into alias. [1] https://github.com/riscv-non-isa/riscv-asm-manual/pull/124
2025-04-28Regenerate more configury files for 64-bit BFD detection fixMaciej W. Rozycki1-3/+0
The fix for 64-bit BFD detection omitted the regeneration of a bunch of configury files; fix that.
2025-04-28Fix 64-bit BFD detection causing build failuresMaciej W. Rozycki2-255/+34
We have a discrepancy with 64-bit BFD handling across our component subdirectories leading to link failures such as: ld: ../opcodes/.libs/libopcodes.a(disassemble.o): in function `disassembler': disassemble.c:(.text+0x65): undefined reference to `print_insn_alpha' ld: disassemble.c:(.text+0x105): undefined reference to `print_insn_ia64' ld: disassemble.c:(.text+0x11d): undefined reference to `print_insn_loongarch' ld: disassemble.c:(.text+0x1a1): undefined reference to `print_insn_big_mips' [...] with some configurations having a 32-bit host and 64-bit BFD, such as: `--host=i386-linux-gnu --target=riscv64-linux-gnu --enable-targets=all'. This is ultimately due to how 64-bit BFD is enabled for bfd/ itself and other subdirectorses and has been a regression from commit 1d5269c994bf ("unify 64-bit bfd checks"). For bfd/ the BFD_64_BIT autoconf macro from config/bfd64.m4 is used combined with this logic in bfd/configure.ac: case ${host64}-${target64}-${want64} in *true*) wordsize=64 bfd64_libs='$(BFD64_LIBS)' all_backends='$(BFD64_BACKENDS) $(BFD32_BACKENDS)' [...] ;; false-false-false) wordsize=32 all_backends='$(BFD32_BACKENDS)' ;; esac where the value of ${wordsize} switches between 32-bit and 64-bit BFD via these pieces: #define BFD_ARCH_SIZE @wordsize@ and: #if BFD_ARCH_SIZE >= 64 #define BFD64 #endif in bfd/bfd-in.h, which ultimately becomes a part of "bfd.h". Then ${host64} is determined in bfd/configure.ac from the host's word size, via the host's pointer size: if test "x${ac_cv_sizeof_void_p}" = "x8"; then host64=true fi And ${target64} is determined in bfd/configure.ac from the target's word size: if test ${target_size} = 64; then target64=true fi Where multiple targets have been requested with `--enable-targets=all' the presence of any 64-bit target will set "true" here. Finally ${want64} is set according to `--enable-64-bit-bfd' user option with an arrangement involving BFD_64_BIT: BFD_64_BIT if test $enable_64_bit_bfd = yes ; then want64=true else want64=false fi which also, redundantly, checks and sets its result upon the host's word size. Lastly ${want64} is also selectively set by target fragments in bfd/config.bfd, which mostly if not completely overlaps with ${target64} setting as described above. Conversely other subdirectories only rely on BFD_64_BIT, so they fail to notice that BFD is 64-bit and do not enable their 64-bit handling where the host requested is 32-bit and 64-bit BFD has been enabled other than with `--enable-64-bit-bfd'. One consequence is opcodes/disassemble.c enables calls to its numerous own 64-bit backends by checking the BFD64 macro from "bfd.h", however does not actually enable said backends in its Makefile. Hence the link errors quoted above. Address the problem then by moving the `--enable-64-bit-bfd' option back to bfd/configure.ac and remove the call to BFD_64_BIT from there and then rewrite the macro in terms of checking for the presence of BFD64 macro in "bfd.h", which is the canonical way of determining whether BFD is 64-bit or not. Rather than running `grep' directly on ../bfd/bfd-in3.h as the opcodes/ fragment used to before the problematic commit: if grep '#define BFD_ARCH_SIZE 64' ../bfd/bfd-in3.h > /dev/null; then run the preprocessor on "bfd.h", which allows to invoke the macro from configure.ac files placed in subdirectories located at deeper levels, by relying on the preprocessor's search path. This requires however that the invokers rely on `all-bfd' rather than `configure-bfd' for their `configure' invocation stage, because "bfd.h" is made by `make all' rather than `configure' in bfd/. Do not cache the result of this check however, as reconfiguring a tree such as to flip `--enable-64-bit-bfd' on or to change a secondary target may affect BFD64 and we have no access to information about secondary targets in BFD_64_BIT. Also remove the ENABLE_BFD_64_BIT automake conditional, as it's not used anywhere. Last but not least remove the hack from gdb/configure.ac to fail builds for `mips*-*-*' hosts where `--enable-targets=all' has been requested, but `--enable-64-bit-bfd' has not as it's no longer needed. Such builds complete successfully now, having enabled 64-bit BFD implicitly. Tested-By: Guinevere Larsen <guinevere@redhat.com> Tested-By: Luis Machado <luis.machado@arm.com> Approved-By: Alan Modra <amodra@gmail.com> Approved-By: Luis Machado <luis.machado@arm.com>
2025-04-28PowerPC: Support for Prefixed Add Immediate Shifted Instruction (RFC02686)Surya Kumari Jangala1-1/+66
opcodes/ * ppc-opc.c (insert_si32, extract_si32, insert_nsi32, extract_nsi32): New functions. (SI32, NSI32, P_D_SI32_MASK, P_DRAPCREL_SI32_MASK): New macros. (IMM32): Update for new macros. (powerpc_opcodes): Add plis, paddis, psubis. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2025-04-15RISC-V: Add missing disassembler option `max`Marek Pikuła1-1/+5
The flag already exists but it's not been exposed to user. Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
2025-04-14x86: move PadLock enumeratorsJan Beulich4-31/+31
... to be all in one group. This helps code generation for code like || is_cpu (&i.tm, CpuPadLock) || is_cpu (&i.tm, CpuPadLockRNG2) || is_cpu (&i.tm, CpuPadLockPHE2) || is_cpu (&i.tm, CpuPadLockXMODX) that we have (effectively) twice.
2025-04-13LoongArch: Support LA32R aliases rdcnt{vl,vh,id}.wWANG Xuerui1-0/+6
These LA32R instructions are in fact special cases of the LA32S/LA64 rdtime{l,h}.w (with only one output operand instead of two, the other one being forced to $zero), but are named differently in the LA32R ISA manual nevertheless. As the LA32R names are more memorable to a degree (especially for those having difficulties remembering which operand corresponds to the node ID), support them by making them aliases of the corresponding LA32S/LA64 instruction respectively, and make them render as such in disassembly. Signed-off-by: WANG Xuerui <git@xen0n.name>
2025-04-09s390: Add support for z17 as CPU nameJens Remus1-1/+2
So far IBM z17 was identified as arch15. Add the real name, as it has been announced. [1] [1]: IBM z17 announcement letter, AD25-0015, https://www.ibm.com/docs/en/announcements/z17-makes-more-possible gas/ * config/tc-s390.c (s390_parse_cpu): Add z17 as alternate CPU name for arch15. * doc/c-s390.texi: Likewise. * doc/as.texi: Likewise. opcodes/ * s390-mkopc.c (main): Add z17 as alternate CPU name for arch15. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-03-29x86: Add {noimm8s} pseudo prefixH.J. Lu4-173/+185
Instruction templates with only sign-extended 8-bit immediate operand also have a second template with full-operand-size immediate operand under a different opcode. Add {noimm8s} pseudo prefix to exclude templates with only sign-extended 8-bit immediate operand. gas/ PR gas/32811 * config/tc-i386.c (pseudo_prefixes): Add no_imm8s. (operand_size_match): Return false for templates with only sign- extended 8-bit immediate operand if {noimm8s} is used. (parse_insn): Handle Prefix_NoImm8s. * doc/c-i386.texi: Document {noimm8s}. * testsuite/gas/i386/pseudos.s: Add tests for {noimm8s}. * testsuite/gas/i386/x86-64-pseudos.s: Likewise. * testsuite/gas/i386/pseudos.d: Updated. * testsuite/gas/i386/x86-64-pseudos.d: Likewise. opcodes/ PR gas/32811 * opcodes/i386-opc.h (Prefix_NoImm8s): New. * i386-opc.tbl: Add {noimm8s} pseudo prefix. * i386-mnem.h: Regenerated. * i386-tbl.h: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-03-28RISC-V: Don't show support for 1.9.1 priv specMarek Pikuła1-3/+6
The privileged spec 1.9.1 support was removed since binutils 2.43. The linker only recognizes it and then reports a warning that it may conflict with other spec versions. While the support is removed, binutils should still recognize it, but it shouldn't be exposed to the user in `disassember-options` help. Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
2025-03-27x86: Remove AVX10.2 256 bit rounding supportHaochen Jiang3-93/+82
Since we will support 512 bit on both P-core and E-core for AVX10, 256 bit rounding is not that useful because we currently have rounding feature directly on E-core now and no need to use 256-bit rounding as somehow a workaround. This patch will remove all the support and backport to Binutils 2.44. gas/ChangeLog: * NEWS: Mention support removal. * config/tc-i386.c (build_evex_prefix): Remove U bit encode. (check_VecOperands): Remove ymm check for rounding. (s_insn): Revise .insn comment. * testsuite/gas/i386/avx10_2-256-cvt-intel.d: Remove ymm rounding related test. * testsuite/gas/i386/avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/avx10_2-256-miscs-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/evex.d: Ditto. * testsuite/gas/i386/evex.s: Ditto. * testsuite/gas/i386/i386.exp: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-miscs.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-satcvt.s: Ditto. * testsuite/gas/i386/x86-64-evex.d: Ditto. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-rounding-intel.d: Removed. * testsuite/gas/i386/avx10_2-rounding-inval.l: Removed. * testsuite/gas/i386/avx10_2-rounding-inval.s: Remo