RISC-V: Fix scalar code-gen of unsigned SAT_MULHEADtrunkmaster

The previous code-gen of scalar unsigned SAT_MUL, aka usmul.
Leverage the mulhs by mistake, it should be mulhu for the
hight bit result of mul.  Thus, this patch would like to make
it correct.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_xmode_usmul): Take
	umulhu for high bits mul result.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c: Add mulhu
	asm check.
	* gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions