RISC-V: Add patterns for vector-scalar IEEE floating-point min

This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into an unspec_vfmin RTL instruction.

Before this patch, we have two instructions, e.g.:
  vfmv.v.f       v2,fa0
  vfmin.vv       v1,v1,v2

After, we get only one:
  vfmin.vf       v1,v1,fa0

gcc/ChangeLog:

	* config/riscv/autovec-opt.md
	(*vfmin_vf_ieee_<mode>): Add new patterns to combine vec_duplicate +
	vfmin.vv (unspec) into vfmin.vf.
	(*vfmul_vf_<mode>, *vfrdiv_vf_<mode>, *vfmin_vf_<mode>): Fix attribute
	types.
	* config/riscv/vector.md (@pred_<ieee_fmaxmin_op><mode>_scalar): Allow
	VLS modes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Add vfmin.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-5-f64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-6-f64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-7-f64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-8-f64.c: New test.

0 files changed, 0 insertions, 0 deletions