RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on GR2VR cost

This patch would like to combine the vec_duplicate + vnmsac.vv to the
vnmsac.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have example code like below, GR2VR cost is 0.

  #define DEF_VX_TERNARY_CASE_0(T, OP_1, OP_2, NAME)
\
  void
\
  test_vx_ternary_##NAME##_##T##_case_0 (T * restrict vd, T * restrict
vs2, \NAME                                         T rs1, unsigned n)
\
  {
\
    for (unsigned i = 0; i < n; i++)
\
      vd[i] = vd[i] OP_2 vs2[i] OP_1 rs1;
\
  }

  DEF_VX_TERNARY_CASE_0(int32_t, *, +, macc)

Before this patch:
  11   │     beq a3,zero,.L8
  12   │     vsetvli a5,zero,e32,m1,ta,ma
  13   │     vmv.v.x v2,a2
  ...
  16   │ .L3:
  17   │     vsetvli a5,a3,e32,m1,ta,ma
  ...
  22   │     vnmsac.vv v1,v2,v3
  ...
  25   │     bne a3,zero,.L3

After this patch:
  11   │     beq a3,zero,.L8
  ...
  14   │ .L3:
  15   │     vsetvli a5,a3,e32,m1,ta,ma
  ...
  20   │     vnmsac.vx v1,a2,v3
  ...
  23   │     bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*vnmsac_vx_<mode>): Add new
	pattern to combine to vx.
	* config/riscv/vector.md (@pred_vnmsac_vx_<mode>): Add new
	pattern to generate rtl.
	(*pred_nmsac_<mode>_scalar_undef): Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions