RISC-V: Support RVV VFSUB and VFRSUB rounding mode intrinsic API

This patch would like to support the rounding mode API for both the
VFSUB and VFRSUB as below samples.

* __riscv_vfsub_vv_f32m1_rm
* __riscv_vfsub_vv_f32m1_rm_m
* __riscv_vfsub_vf_f32m1_rm
* __riscv_vfsub_vf_f32m1_rm_m
* __riscv_vfrsub_vf_f32m1_rm
* __riscv_vfrsub_vf_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class reverse_binop_frm): Add new template for reversed frm.
	(vfsub_frm_obj): New obj.
	(vfrsub_frm_obj): Likewise.
	* config/riscv/riscv-vector-builtins-bases.h:
	(vfsub_frm): New declaration.
	(vfrsub_frm): Likewise.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfsub_frm): New function define.
	(vfrsub_frm): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-single-rsub.c: New test.
	* gcc.target/riscv/rvv/base/float-point-single-sub.c: New test.

0 files changed, 0 insertions, 0 deletions