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authorMartin Liska <mliska@suse.cz>2016-03-24 14:04:12 +0100
committerMartin Liska <marxin@gcc.gnu.org>2016-03-24 13:04:12 +0000
commitf9c8babbab276ba1593e201c5ce533b3216aea56 (patch)
treeae7e8fb917ef1ed5af713a7fc654c7468ed7c233 /libgomp/plugin
parented87de55831955ee08398a3c5641ba92d31a39f1 (diff)
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Properly assign to packet header (PR hsa/70394)
* plugin/plugin-hsa.c (packet_store_release): New function that is taken from the HSA runtime manual. (GOMP_OFFLOAD_run): Use the function. From-SVN: r234454
Diffstat (limited to 'libgomp/plugin')
-rw-r--r--libgomp/plugin/plugin-hsa.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/libgomp/plugin/plugin-hsa.c b/libgomp/plugin/plugin-hsa.c
index f7ef600..0b3b67a 100644
--- a/libgomp/plugin/plugin-hsa.c
+++ b/libgomp/plugin/plugin-hsa.c
@@ -1185,6 +1185,14 @@ failure:
return false;
}
+/* Atomically store pair of uint16_t values (HEADER and REST) to a PACKET. */
+
+void
+packet_store_release (uint32_t* packet, uint16_t header, uint16_t rest)
+{
+ __atomic_store_n (packet, header | (rest << 16), __ATOMIC_RELEASE);
+}
+
/* Part of the libgomp plugin interface. Run a kernel on device N and pass it
an array of pointers in VARS as a parameter. The kernel is identified by
FN_PTR which must point to a kernel_info structure. */
@@ -1232,7 +1240,6 @@ GOMP_OFFLOAD_run (int n, void *fn_ptr, void *vars, void **args)
+ index % agent->command_q->size;
memset (((uint8_t *) packet) + 4, 0, sizeof (*packet) - 4);
- packet->setup |= (uint16_t) 1 << HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS;
packet->grid_size_x = kla->gdims[0];
uint32_t wgs = kla->wdims[0];
if (wgs == 0)
@@ -1275,7 +1282,9 @@ GOMP_OFFLOAD_run (int n, void *fn_ptr, void *vars, void **args)
HSA_DEBUG ("Going to dispatch kernel %s\n", kernel->name);
- __atomic_store_n ((uint16_t *) (&packet->header), header, __ATOMIC_RELEASE);
+ packet_store_release ((uint32_t *) packet, header,
+ 1 << HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS);
+
hsa_signal_store_release (agent->command_q->doorbell_signal, index);
/* TODO: GPU agents in Carrizo APUs cannot properly update L2 cache for