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| author | Andrew Stubbs <ams@baylibre.com> | 2024-01-24 11:07:28 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@baylibre.com> | 2024-01-26 11:38:47 +0000 |
| commit | 99890e15527f1f04caef95ecdd135c9f1a077f08 (patch) | |
| tree | 4c1e9e6745f733e8fb616c5f9388fedce1a9c51c /libgomp/config | |
| parent | a0dde47f84f17cbe7fa2fb41c14c5a2db8c4d63a (diff) | |
| download | gcc-99890e15527f1f04caef95ecdd135c9f1a077f08.zip gcc-99890e15527f1f04caef95ecdd135c9f1a077f08.tar.gz gcc-99890e15527f1f04caef95ecdd135c9f1a077f08.tar.bz2 | |
amdgcn: additional gfx1030/gfx1100 support
This is enough to get gfx1030 and gfx1100 working; there are still some test
failures to investigate, and probably some tuning to do.
gcc/ChangeLog:
* config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
* config/gcn/gcn-valu.md (all_convert): New iterator.
(<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
define_expand, and rename the old one to ...
(*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
(extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
(extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
(*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
* config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
(gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
* config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
(<u>mulqihi3_scalar): Likewise.
libgcc/ChangeLog:
* config/gcn/amdgcn_veclib.h (CDNA3_PLUS): Handle RDNA3.
libgomp/ChangeLog:
* config/gcn/time.c (RTC_TICKS): Configure RDNA3.
(omp_get_wtime): Add RDNA3-compatible variant.
* plugin/plugin-gcn.c (max_isa_vgprs): Tune for gfx1030 and gfx1100.
Signed-off-by: Andrew Stubbs <ams@baylibre.com>
Diffstat (limited to 'libgomp/config')
| -rw-r--r-- | libgomp/config/gcn/time.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/libgomp/config/gcn/time.c b/libgomp/config/gcn/time.c index 30a0d01..efcd04f 100644 --- a/libgomp/config/gcn/time.c +++ b/libgomp/config/gcn/time.c @@ -30,15 +30,25 @@ /* According to AMD: dGPU RTC is 27MHz AGPU RTC is 100MHz + RDNA3 ISA manual states "typically 100MHz" FIXME: DTRT on an APU. */ +#ifdef __RDNA3__ +#define RTC_TICKS (1.0 / 100000000.0) /* 100MHz */ +#else #define RTC_TICKS (1.0 / 27000000.0) /* 27MHz */ +#endif double omp_get_wtime (void) { uint64_t clock; +#ifdef __RDNA3__ + asm ("s_sendmsg_rtn_b64 %0 0x83 ;Get REALTIME\n\t" + "s_waitcnt 0" : "=r" (clock)); +#else asm ("s_memrealtime %0\n\t" "s_waitcnt 0" : "=r" (clock)); +#endif return clock * RTC_TICKS; } |