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authorThomas Preud'homme <thomas.preudhomme@arm.com>2016-11-16 18:30:56 +0000
committerThomas Preud'homme <thopre01@gcc.gnu.org>2016-11-16 18:30:56 +0000
commit660e6c2c127fdec06bfa428b08ab4123e37281a5 (patch)
tree0e26028c9bf60b7ec7247434464570e6f1dc6643 /libgo/go
parent5e8d7713becd848449a35231d58b8b0965467784 (diff)
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Fix ICE on empty FIQ interrupt handler on ARM
2016-11-16 Thomas Preud'homme <thomas.preudhomme@arm.com> gcc/ * config/arm/arm.md (arm_addsi3): Add alternative for addition of general register with general register or ARM constant into SP register. gcc/testsuite/ * gcc.target/arm/empty_fiq_handler.c: New test. From-SVN: r242508
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