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authorJin Ma <jinma@linux.alibaba.com>2025-02-11 21:28:05 +0800
committerJin Ma <jinma@linux.alibaba.com>2025-02-12 10:21:09 +0800
commit580f571be6ce80aa71fb80e7b16e01824f088229 (patch)
tree3e9cfe387cfb0878256990691c6453c9ae524ac4 /libgo/go/net/mail/example_test.go
parent805329e09cede41209f6c3502fa2c17aefffe91b (diff)
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RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targetsHEADtrunkmaster
This is a follow-up to the patch below to avoid generating unrecognized vsetivl instructions for XTheadVector. https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674185.html PR target/118601 gcc/ChangeLog: * config/riscv/riscv-string.cc (expand_block_move): Check with new constraint 'vl' instead of 'K'. (expand_vec_setmem): Likewise. (expand_vec_cmpmem): Likewise. * config/riscv/riscv-v.cc (force_vector_length_operand): Likewise. (expand_load_store): Likewise. (expand_strided_load): Likewise. (expand_strided_store): Likewise. (expand_lanes_load_store): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/pr114194.c: Move to... * gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c: ...here. * gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c: New test. * gcc.target/riscv/rvv/xtheadvector/pr118601.c: New test. Reported-by: Edwin Lu <ewlu@rivosinc.com>
Diffstat (limited to 'libgo/go/net/mail/example_test.go')
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