libgo: update to go1.15rc1

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/245157

6 files changed, 66 insertions, 37 deletions

diff --git a/libgo/go/internal/cpu/cpu.go b/libgo/go/internal/cpu/cpu.go
index f326b06..2829945 100644
--- a/libgo/go/internal/cpu/cpu.go
+++ b/libgo/go/internal/cpu/cpu.go
@@ -19,13 +19,11 @@ type CacheLinePad struct{ _ [CacheLinePadSize]byte }
 // so we use the constant per GOARCH CacheLinePadSize as an approximation.
 var CacheLineSize uintptr = CacheLinePadSize
 
-var X86 x86
-
-// The booleans in x86 contain the correspondingly named cpuid feature bit.
+// The booleans in X86 contain the correspondingly named cpuid feature bit.
 // HasAVX and HasAVX2 are only set if the OS does support XMM and YMM registers
 // in addition to the cpuid feature bit being set.
 // The struct is padded to avoid false sharing.
-type x86 struct {
+var X86 struct {
 	_            CacheLinePad
 	HasAES       bool
 	HasADX       bool
@@ -46,38 +44,18 @@ type x86 struct {
 	_            CacheLinePad
 }
 
-var PPC64 ppc64
-
-// For ppc64(le), it is safe to check only for ISA level starting on ISA v3.00,
-// since there are no optional categories. There are some exceptions that also
-// require kernel support to work (darn, scv), so there are feature bits for
-// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
-// The struct is padded to avoid false sharing.
-type ppc64 struct {
-	_        CacheLinePad
-	HasDARN  bool // Hardware random number generator (requires kernel enablement)
-	HasSCV   bool // Syscall vectored (requires kernel enablement)
-	IsPOWER8 bool // ISA v2.07 (POWER8)
-	IsPOWER9 bool // ISA v3.00 (POWER9)
-	_        CacheLinePad
-}
-
-var ARM arm
-
-// The booleans in arm contain the correspondingly named cpu feature bit.
+// The booleans in ARM contain the correspondingly named cpu feature bit.
 // The struct is padded to avoid false sharing.
-type arm struct {
+var ARM struct {
 	_        CacheLinePad
 	HasVFPv4 bool
 	HasIDIVA bool
 	_        CacheLinePad
 }
 
-var ARM64 arm64
-
-// The booleans in arm64 contain the correspondingly named cpu feature bit.
+// The booleans in ARM64 contain the correspondingly named cpu feature bit.
 // The struct is padded to avoid false sharing.
-type arm64 struct {
+var ARM64 struct {
 	_           CacheLinePad
 	HasFP       bool
 	HasASIMD    bool
@@ -106,9 +84,27 @@ type arm64 struct {
 	_           CacheLinePad
 }
 
-var S390X s390x
+var MIPS64X struct {
+	_      CacheLinePad
+	HasMSA bool // MIPS SIMD architecture
+	_      CacheLinePad
+}
+
+// For ppc64(le), it is safe to check only for ISA level starting on ISA v3.00,
+// since there are no optional categories. There are some exceptions that also
+// require kernel support to work (darn, scv), so there are feature bits for
+// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
+// The struct is padded to avoid false sharing.
+var PPC64 struct {
+	_        CacheLinePad
+	HasDARN  bool // Hardware random number generator (requires kernel enablement)
+	HasSCV   bool // Syscall vectored (requires kernel enablement)
+	IsPOWER8 bool // ISA v2.07 (POWER8)
+	IsPOWER9 bool // ISA v3.00 (POWER9)
+	_        CacheLinePad
+}
 
-type s390x struct {
+var S390X struct {
 	_         CacheLinePad
 	HasZARCH  bool // z architecture mode is active [mandatory]
 	HasSTFLE  bool // store facility list extended [mandatory]
diff --git a/libgo/go/internal/cpu/cpu_arm.go b/libgo/go/internal/cpu/cpu_arm.go
index a1d5a7b..7324e7b 100644
--- a/libgo/go/internal/cpu/cpu_arm.go
+++ b/libgo/go/internal/cpu/cpu_arm.go
@@ -5,9 +5,8 @@
 package cpu
 
 // arm doesn't have a 'cpuid' equivalent, so we rely on HWCAP/HWCAP2.
-// These are linknamed in runtime/os_(linux|freebsd)_arm.go and are
-// initialized by archauxv().
-// These should not be changed after they are initialized.
+// These are initialized by archauxv() and should not be changed after they are
+// initialized.
 var HWCap uint
 var HWCap2 uint
 
diff --git a/libgo/go/internal/cpu/cpu_arm64.go b/libgo/go/internal/cpu/cpu_arm64.go
index 99fa991..c1f0b01 100644
--- a/libgo/go/internal/cpu/cpu_arm64.go
+++ b/libgo/go/internal/cpu/cpu_arm64.go
@@ -5,8 +5,8 @@
 package cpu
 
 // arm64 doesn't have a 'cpuid' equivalent, so we rely on HWCAP/HWCAP2.
-// These are initialized by archauxv in runtime/os_linux_arm64.go.
-// These should not be changed after they are initialized.
+// These are initialized by archauxv and should not be changed after they are
+// initialized.
 var HWCap uint
 var HWCap2 uint
 
diff --git a/libgo/go/internal/cpu/cpu_mips64x.go b/libgo/go/internal/cpu/cpu_mips64x.go
new file mode 100644
index 0000000..0c4794a
--- /dev/null
+++ b/libgo/go/internal/cpu/cpu_mips64x.go
@@ -0,0 +1,32 @@
+// Copyright 2019 The Go Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// +build mips64 mips64le
+
+package cpu
+
+const CacheLinePadSize = 32
+
+// This is initialized by archauxv and should not be changed after it is
+// initialized.
+var HWCap uint
+
+// HWCAP bits. These are exposed by the Linux kernel 5.4.
+const (
+	// CPU features
+	hwcap_MIPS_MSA = 1 << 1
+)
+
+func doinit() {
+	options = []option{
+		{Name: "msa", Feature: &MIPS64X.HasMSA},
+	}
+
+	// HWCAP feature bits
+	MIPS64X.HasMSA = isSet(HWCap, hwcap_MIPS_MSA)
+}
+
+func isSet(hwc uint, value uint) bool {
+	return hwc&value != 0
+}
diff --git a/libgo/go/internal/cpu/cpu_no_init.go b/libgo/go/internal/cpu/cpu_no_init.go
index d4b2be8..fb381e1 100644
--- a/libgo/go/internal/cpu/cpu_no_init.go
+++ b/libgo/go/internal/cpu/cpu_no_init.go
@@ -9,6 +9,8 @@
 // +build !ppc64
 // +build !ppc64le
 // +build !s390x
+// +build !mips64
+// +build !mips64le
 
 package cpu
 
diff --git a/libgo/go/internal/cpu/cpu_ppc64x.go b/libgo/go/internal/cpu/cpu_ppc64x.go
index 02f2c06..b726cc8 100644
--- a/libgo/go/internal/cpu/cpu_ppc64x.go
+++ b/libgo/go/internal/cpu/cpu_ppc64x.go
@@ -7,8 +7,8 @@
 package cpu
 
 // ppc64x doesn't have a 'cpuid' equivalent, so we rely on HWCAP/HWCAP2.
-// These are initialized by archauxv in runtime/os_linux_ppc64x.go.
-// These should not be changed after they are initialized.
+// These are initialized by archauxv and should not be changed after they are
+// initialized.
 // On aix/ppc64, these values are initialized early in the runtime in runtime/os_aix.go.
 var HWCap uint
 var HWCap2 uint