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| author | Maciej W. Rozycki <macro@wdc.com> | 2020-08-28 16:05:56 +0100 |
|---|---|---|
| committer | Ian Lance Taylor <iant@golang.org> | 2020-09-30 19:47:48 -0700 |
| commit | 2c5499b57cf4a68ebc8decce90d3eb1e281c31a9 (patch) | |
| tree | a53f1214796df28a6c081cdcd556c5bdd1bda5c9 /libgo/go/golang.org/x/sys | |
| parent | 2dd7b93778d551b6981c8086ecb38e26f677bd2b (diff) | |
| download | gcc-2c5499b57cf4a68ebc8decce90d3eb1e281c31a9.zip gcc-2c5499b57cf4a68ebc8decce90d3eb1e281c31a9.tar.gz gcc-2c5499b57cf4a68ebc8decce90d3eb1e281c31a9.tar.bz2 | |
libgo: add 32-bit RISC-V (RV32) support
Add support for the 32-bit RISC-V (RV32) ISA matching the 64-bit RISC-V
(RV64) port except for async preemption added as a stub only.
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/251179
Diffstat (limited to 'libgo/go/golang.org/x/sys')
| -rw-r--r-- | libgo/go/golang.org/x/sys/cpu/cpu_riscv.go | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/libgo/go/golang.org/x/sys/cpu/cpu_riscv.go b/libgo/go/golang.org/x/sys/cpu/cpu_riscv.go new file mode 100644 index 0000000..891cb98 --- /dev/null +++ b/libgo/go/golang.org/x/sys/cpu/cpu_riscv.go @@ -0,0 +1,7 @@ +// Copyright 2020 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// +build riscv + +package cpu |