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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2023-02-20 14:54:45 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-02-22 20:51:21 +0800 |
| commit | c878c6586dee353e685364910e02ad1a611d4634 (patch) | |
| tree | e78e2820be653b966d4dcb1f041ada2d8215a223 /libgcc | |
| parent | dc244cdc05a0cc4a7c40c5c5027c12cc1dc6e4d3 (diff) | |
| download | gcc-c878c6586dee353e685364910e02ad1a611d4634.zip gcc-c878c6586dee353e685364910e02ad1a611d4634.tar.gz gcc-c878c6586dee353e685364910e02ad1a611d4634.tar.bz2 | |
RISC-V: Add RVV reduction C/C++ intrinsics support
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (class reducop): New class.
(class widen_reducop): Ditto.
(class freducop): Ditto.
(class widen_freducop): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vredsum): Add reduction support.
(vredmaxu): Ditto.
(vredmax): Ditto.
(vredminu): Ditto.
(vredmin): Ditto.
(vredand): Ditto.
(vredor): Ditto.
(vredxor): Ditto.
(vwredsum): Ditto.
(vwredsumu): Ditto.
(vfredusum): Ditto.
(vfredosum): Ditto.
(vfredmax): Ditto.
(vfredmin): Ditto.
(vfwredosum): Ditto.
(vfwredusum): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct reduc_alu_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_WI_OPS): New macro.
(DEF_RVV_WU_OPS): Ditto.
(DEF_RVV_WF_OPS): Ditto.
(vint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint8mf8_t): Ditto.
(vuint8mf4_t): Ditto.
(vuint8mf2_t): Ditto.
(vuint8m1_t): Ditto.
(vuint8m2_t): Ditto.
(vuint8m4_t): Ditto.
(vuint8m8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_WI_OPS): Ditto.
(DEF_RVV_WU_OPS): Ditto.
(DEF_RVV_WF_OPS): Ditto.
(required_extensions_p): Add reduction support.
(rvv_arg_type_info::get_base_vector_type): Ditto.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Ditto.
* config/riscv/riscv.md: Ditto.
* config/riscv/vector-iterators.md (minu): Ditto.
* config/riscv/vector.md (@pred_reduc_<reduc><mode><vlmul1>): New patern.
(@pred_reduc_<reduc><mode><vlmul1_zve32>): Ditto.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Ditto.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>):Ditto.
(@pred_reduc_plus<order><mode><vlmul1>): Ditto.
(@pred_reduc_plus<order><mode><vlmul1_zve32>): Ditto.
(@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
Diffstat (limited to 'libgcc')
0 files changed, 0 insertions, 0 deletions