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authorEric Botcazou <ebotcazou@adacore.com>2013-05-28 13:52:50 +0000
committerEric Botcazou <ebotcazou@gcc.gnu.org>2013-05-28 13:52:50 +0000
commit0ba045df8f42f2af5e15a0f28f1beeaa18acaa44 (patch)
tree7d46615086d4d141883c11329608649fdbc7f160 /libgcc/config
parentfbd7e8773135e1912e36d22e0a9c9a4e6e78c43f (diff)
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sol2-unwind.h (MD_FALLBACK_FRAME_STATE_FOR): Do not set fs->signal_frame for SIGFPE raised for IEEE-754 exceptions.
* config/sparc/sol2-unwind.h (MD_FALLBACK_FRAME_STATE_FOR): Do not set fs->signal_frame for SIGFPE raised for IEEE-754 exceptions. * config/i386/sol2-unwind.h (x86_fallback_frame_state): Likewise. From-SVN: r199381
Diffstat (limited to 'libgcc/config')
-rw-r--r--libgcc/config/i386/sol2-unwind.h7
-rw-r--r--libgcc/config/sparc/sol2-unwind.h7
2 files changed, 12 insertions, 2 deletions
diff --git a/libgcc/config/i386/sol2-unwind.h b/libgcc/config/i386/sol2-unwind.h
index f804aaf..e677109 100644
--- a/libgcc/config/i386/sol2-unwind.h
+++ b/libgcc/config/i386/sol2-unwind.h
@@ -249,7 +249,12 @@ x86_fallback_frame_state (struct _Unwind_Context *context,
fs->regs.reg[8].how = REG_SAVED_OFFSET;
fs->regs.reg[8].loc.offset = (long)&mctx->gregs[EIP] - new_cfa;
fs->retaddr_column = 8;
- fs->signal_frame = 1;
+
+ /* SIGFPE for IEEE-754 exceptions is delivered after the faulting insn
+ rather than before it, so don't set fs->signal_frame in that case.
+ We test whether the ES field of the Status Register is zero. */
+ if ((mctx->fpregs.fp_reg_set.fpchip_state.status & 0x80) == 0)
+ fs->signal_frame = 1;
return _URC_NO_REASON;
}
diff --git a/libgcc/config/sparc/sol2-unwind.h b/libgcc/config/sparc/sol2-unwind.h
index 584a9b0..4a8c42f5 100644
--- a/libgcc/config/sparc/sol2-unwind.h
+++ b/libgcc/config/sparc/sol2-unwind.h
@@ -403,7 +403,12 @@ MD_FALLBACK_FRAME_STATE_FOR (struct _Unwind_Context *context,
fs->retaddr_column = 0;
fs->regs.reg[0].how = REG_SAVED_OFFSET;
fs->regs.reg[0].loc.offset = (long)shifted_ra_location - new_cfa;
- fs->signal_frame = 1;
+
+ /* SIGFPE for IEEE-754 exceptions is delivered after the faulting insn
+ rather than before it, so don't set fs->signal_frame in that case.
+ We test whether the cexc field of the FSR is zero. */
+ if ((mctx->fpregs.fpu_fsr & 0x1f) == 0)
+ fs->signal_frame = 1;
return _URC_NO_REASON;
}