RISC-V: Add --with-cmodel configure option

Sometimes we want to use default cmodel other than medlow. Add a GCC
configure option for that.

gcc/ChangeLog:

	* config.gcc (riscv*-*-*): Add support for --with-cmodel configure option.
	(all_defaults): Add cmodel.
	* config/riscv/riscv.h (TARGET_DEFAULT_CMODEL): Remove.
	* doc/install.texi: Document --with-cmodel configure option.
	* doc/invoke.texi (-mcmodel): Mention --with-cmodel configure option.

Co-authored-by: Kito Cheng <kito.cheng@sifive.com>

4 files changed, 29 insertions, 6 deletions

diff --git a/gcc/config.gcc b/gcc/config.gcc
index afa7845..f4ae14c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4711,7 +4711,7 @@ case "${target}" in
 		;;
 
 	riscv*-*-*)
-		supported_defaults="abi arch tune riscv_attribute isa_spec tls"
+		supported_defaults="abi arch tune riscv_attribute isa_spec tls cmodel"
 
 		case "${target}" in
 		riscv-* | riscv32*) xlen=32 ;;
@@ -4867,6 +4867,25 @@ case "${target}" in
 				exit 1
 			esac
 		fi
+
+		# Handle --with-cmodel.
+		# Make sure --with-cmodel is valid.  If it was not specified,
+		# use medlow as the default value.
+		case "${with_cmodel}" in
+		"" | medlow)
+			tm_defines="${tm_defines} TARGET_DEFAULT_CMODEL=CM_MEDLOW"
+			;;
+		medany)
+			tm_defines="${tm_defines} TARGET_DEFAULT_CMODEL=CM_MEDANY"
+			;;
+		large)
+			tm_defines="${tm_defines} TARGET_DEFAULT_CMODEL=CM_LARGE"
+			;;
+		*)
+			echo "invalid option for --with-cmodel: '${with_cmodel}', available values are 'medlow' 'medany' 'large'" 1>&2
+			exit 1
+			;;
+		esac
 		;;
 
 	mips*-*-*)
@@ -6046,7 +6065,7 @@ case ${target} in
 esac
 
 t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec compact-branches msa"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt synci tls lxc1-sxc1 madd4 isa_spec compact-branches msa cmodel"
 for option in $all_defaults
 do
 	eval "val=\$with_"`echo $option | sed s/-/_/g`
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 8a8b08b..09de746 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -119,8 +119,6 @@ ASM_MISA_SPEC
 "%{march=*:%:riscv_expand_arch(%*)} "				\
 "%{!march=*:%{mcpu=*:%:riscv_expand_arch_from_cpu(%*)}} "
 
-#define TARGET_DEFAULT_CMODEL CM_MEDLOW
-
 #define LOCAL_LABEL_PREFIX	"."
 #define USER_LABEL_PREFIX	""
 
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index 97d9aaf..4107697 100644
--- a/gcc/doc/install.texi
+++ b/gcc/doc/install.texi
@@ -1537,6 +1537,10 @@ Use big endian by default.  Provide a multilib for little endian.
 Use little endian by default.  Provide a multilib for big endian.
 @end table
 
+@item --with-cmodel=@var{cmodel}
+Specify what code model to use by default.
+Currently only implemented for riscv*-*-*.
+
 @item --enable-threads
 Specify that the target
 supports threads.  This affects the Objective-C compiler and runtime
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e85a149..80eaeb9 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -31104,8 +31104,10 @@ element-misaligned vector memory access.
 @item -mcmodel=medlow
 Generate code for the medium-low code model. The program and its statically
 defined symbols must lie within a single 2 GiB address range and must lie
-between absolute addresses @minus{}2 GiB and +2 GiB. Programs can be
-statically or dynamically linked. This is the default code model.
+between absolute addresses @minus{}2 GiB and +2 GiB. Programs can be statically
+or dynamically linked. This is the default code model unless GCC has been
+configured with @option{--with-cmodel=} specifying a different default code
+model.
 
 @opindex mcmodel=medany
 @item -mcmodel=medany