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author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-12-12 10:06:38 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2023-12-12 10:09:34 +0800 |
commit | fda2e1ab60377ca1a6aff093355b29115cff5880 (patch) | |
tree | 45ba9e8cff14dc1d9ec9f630749b8a1c1a0de741 /gcc | |
parent | 4b421728289e6f1caa0dfaa953a11698ab95d37d (diff) | |
download | gcc-fda2e1ab60377ca1a6aff093355b29115cff5880.zip gcc-fda2e1ab60377ca1a6aff093355b29115cff5880.tar.gz gcc-fda2e1ab60377ca1a6aff093355b29115cff5880.tar.bz2 |
RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC]
This patch moves RVV POLY VALUE estimation from riscv.cc to riscv-v.cc for
future better maintain like other target hook implementation.
Committed as it is obviously a code refinement.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (estimated_poly_value): New function.
* config/riscv/riscv-v.cc (estimated_poly_value): Ditto.
* config/riscv/riscv.cc (riscv_estimated_poly_value): Move RVV POLY
VALUE estimation to riscv-v.cc
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/riscv-protos.h | 1 | ||||
-rw-r--r-- | gcc/config/riscv/riscv-v.cc | 47 | ||||
-rw-r--r-- | gcc/config/riscv/riscv.cc | 44 |
3 files changed, 52 insertions, 40 deletions
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 20bbb5b..85ab1db 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -608,6 +608,7 @@ int count_regno_occurrences (rtx_insn *, unsigned int); bool imm_avl_p (machine_mode); bool can_be_broadcasted_p (rtx); bool gather_scatter_valid_offset_p (machine_mode); +HOST_WIDE_INT estimated_poly_value (poly_int64, unsigned int); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 944b37b..01898cb 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4927,4 +4927,51 @@ gather_scatter_valid_offset_p (machine_mode mode) return true; } +/* Implement TARGET_ESTIMATED_POLY_VALUE. + Look into the tuning structure for an estimate. + KIND specifies the type of requested estimate: min, max or likely. + For cores with a known VLA width all three estimates are the same. + For generic VLA tuning we want to distinguish the maximum estimate from + the minimum and likely ones. + The likely estimate is the same as the minimum in that case to give a + conservative behavior of auto-vectorizing with VLA when it is a win + even for VLA vectorization. + When VLA width information is available VAL.coeffs[1] is multiplied by + the number of VLA chunks over the initial VLS bits. */ +HOST_WIDE_INT +estimated_poly_value (poly_int64 val, unsigned int kind) +{ + unsigned int width_source + = BITS_PER_RISCV_VECTOR.is_constant () + ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () + : (unsigned int) RVV_SCALABLE; + + /* If there is no core-specific information then the minimum and likely + values are based on TARGET_MIN_VLEN vectors and the maximum is based on + the architectural maximum of 65536 bits. */ + unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1; + if (width_source == RVV_SCALABLE) + switch (kind) + { + case POLY_VALUE_MIN: + case POLY_VALUE_LIKELY: + return val.coeffs[0]; + + case POLY_VALUE_MAX: + return val.coeffs[0] + val.coeffs[1] * min_vlen_bytes; + } + + /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the + lowest as likely. This could be made more general if future -mtune + options need it to be. */ + if (kind == POLY_VALUE_MAX) + width_source = 1 << floor_log2 (width_source); + else + width_source = least_bit_hwi (width_source); + + /* If the core provides width information, use that. */ + HOST_WIDE_INT over_min_vlen = width_source - TARGET_MIN_VLEN; + return val.coeffs[0] + val.coeffs[1] * over_min_vlen / TARGET_MIN_VLEN; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3f111fa..69a8a50 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -9604,51 +9604,15 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor, return RISCV_DWARF_VLENB; } -/* Implement TARGET_ESTIMATED_POLY_VALUE. - Look into the tuning structure for an estimate. - KIND specifies the type of requested estimate: min, max or likely. - For cores with a known RVV width all three estimates are the same. - For generic RVV tuning we want to distinguish the maximum estimate from - the minimum and likely ones. - The likely estimate is the same as the minimum in that case to give a - conservative behavior of auto-vectorizing with RVV when it is a win - even for 128-bit RVV. - When RVV width information is available VAL.coeffs[1] is multiplied by - the number of VQ chunks over the initial Advanced SIMD 128 bits. */ +/* Implement TARGET_ESTIMATED_POLY_VALUE. */ static HOST_WIDE_INT riscv_estimated_poly_value (poly_int64 val, poly_value_estimate_kind kind = POLY_VALUE_LIKELY) { - unsigned int width_source = BITS_PER_RISCV_VECTOR.is_constant () - ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () - : (unsigned int) RVV_SCALABLE; - - /* If there is no core-specific information then the minimum and likely - values are based on 128-bit vectors and the maximum is based on - the architectural maximum of 65536 bits. */ - if (width_source == RVV_SCALABLE) - switch (kind) - { - case POLY_VALUE_MIN: - case POLY_VALUE_LIKELY: - return val.coeffs[0]; - - case POLY_VALUE_MAX: - return val.coeffs[0] + val.coeffs[1] * 15; - } - - /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the - lowest as likely. This could be made more general if future -mtune - options need it to be. */ - if (kind == POLY_VALUE_MAX) - width_source = 1 << floor_log2 (width_source); - else - width_source = least_bit_hwi (width_source); - - /* If the core provides width information, use that. */ - HOST_WIDE_INT over_128 = width_source - 128; - return val.coeffs[0] + val.coeffs[1] * over_128 / 128; + if (TARGET_VECTOR) + return riscv_vector::estimated_poly_value (val, kind); + return default_estimated_poly_value (val, kind); } /* Return true if the vector misalignment factor is supported by the |