altivec-12.c (main): Fix declaration of ucz to make it consistent with the naming convention in the file.

gcc/testsuite/ChangeLog:

2018-06-01  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/altivec-12.c (main): Fix declaration of ucz
	to make it consistent with the naming convention in the file.
	* gcc.target/powerpc/altivec-7-be.c: Move BE specific checks
	to altivec-7.c.  Delete file.
	* gcc.target/powerpc/altivec-7-le.c: Move LE specific checks
	to altivec-7.c.  Delete file.
	* gcc.target/powerpc/altivec-7.h: Move to altivec-7.c.
	* gcc.target/powerpc/altivec-7.c (main): Add vec_unpackh and
	vec_unpackl tests.  Update instruction counts.
	* gcc.target/powerpc/builtins-1-le.c: Move LE specific checks to
	tests to builtins-1.c.
	* gcc.target/powerpc/builtins-1-be.c: Move BE specific
	tests to builtins-1.c.
	* gcc.target/powerpc/builtins-1.h: Move to file builtins-1.c.
	* gcc.target/powerpc/builtins-1.c (main): Add test case for vec_and.
	vec_round, vec_rsqrt, vec_rsqrte, vec_mergee, vec_mergh, vec_mergo.
	Remove vec_ctf tests returning double.  Remove vec_cts with
	double args. Remove vec_sel with invalid arguments. Add tests for
	vec_splat.
	Add instruction counts for new tests.
	* gcc.target/powerpc/builtins-3-runnable.c (main): Add test for
	vec_doublee, vec_doubleo, vec_doublel, vec_doubleh, vec_signed,
	vec_unsigned.
	* gcc.target/powerpc/builtins-3.c: Add tests test_sll_vuill_vuill_vuc,
	test_sll_vsill_vsill_vuc.
	* gcc.target/powerpc/p9-xxbr-2.c (rev_bool_long_long): Added test for
	vec_revb.
	* gcc.target/powerpc/vsx-7.h: Rename to vsx-7.c. Remove redundant
	tests from altivec-7.h.
	* gcc.target/powerpc/vsx-7-be.c: Remove file.
	* gcc.target/powerpc/vsx-builtin-7.c: Add test functions splat_sc_s8,
	splat_uc_u8, splat_ssi_s16, splat_usi_s16, splat_si_s32, splat_ui_u32,
	splat_sll, splat_uc, splat_int128, splat_uint128.
	Make second argument of vec_extract and vec_insert a signed int.
	* gcc.target/powerpc/vsx-vector-5.c (vrint): Add vrint test for float
	argument.

From-SVN: r261097

17 files changed, 523 insertions, 422 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b8a5a8b..b2dacc5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,42 @@
+2018-06-01  Carl Love  <cel@us.ibm.com>
+
+	* gcc.target/powerpc/altivec-12.c (main): Fix declaration of ucz
+	to make it consistent with the naming convention in the file.
+	* gcc.target/powerpc/altivec-7-be.c: Move BE specific checks
+	to altivec-7.c.  Delete file.
+	* gcc.target/powerpc/altivec-7-le.c: Move LE specific checks
+	to altivec-7.c.  Delete file.
+	* gcc.target/powerpc/altivec-7.h: Move to altivec-7.c.
+	* gcc.target/powerpc/altivec-7.c (main): Add vec_unpackh and
+	vec_unpackl tests.  Update instruction counts.
+	* gcc.target/powerpc/builtins-1-le.c: Move LE specific checks to
+	tests to builtins-1.c.
+	* gcc.target/powerpc/builtins-1-be.c: Move BE specific
+	tests to builtins-1.c.
+	* gcc.target/powerpc/builtins-1.h: Move to file builtins-1.c.
+	* gcc.target/powerpc/builtins-1.c (main): Add test case for vec_and.
+	vec_round, vec_rsqrt, vec_rsqrte, vec_mergee, vec_mergh, vec_mergo.
+	Remove vec_ctf tests returning double.  Remove vec_cts with
+	double args. Remove vec_sel with invalid arguments. Add tests for
+	vec_splat.
+	Add instruction counts for new tests.
+	* gcc.target/powerpc/builtins-3-runnable.c (main): Add test for
+	vec_doublee, vec_doubleo, vec_doublel, vec_doubleh, vec_signed,
+	vec_unsigned.
+	* gcc.target/powerpc/builtins-3.c: Add tests test_sll_vuill_vuill_vuc,
+	test_sll_vsill_vsill_vuc.
+	* gcc.target/powerpc/p9-xxbr-2.c (rev_bool_long_long): Added test for
+	vec_revb.
+	* gcc.target/powerpc/vsx-7.h: Rename to vsx-7.c. Remove redundant
+	tests from altivec-7.h.
+	* gcc.target/powerpc/vsx-7-be.c: Remove file.
+	* gcc.target/powerpc/vsx-builtin-7.c: Add test functions splat_sc_s8,
+	splat_uc_u8, splat_ssi_s16, splat_usi_s16, splat_si_s32, splat_ui_u32,
+	splat_sll, splat_uc, splat_int128, splat_uint128.
+	Make second argument of vec_extract and vec_insert a signed int.
+	* gcc.target/powerpc/vsx-vector-5.c (vrint): Add vrint test for float
+	argument.
+
 2018-06-01  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gcc.dg/store_merging_20.c: New test.
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-12.c b/gcc/testsuite/gcc.target/powerpc/altivec-12.c
index b0267b5..1f3175f 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-12.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-12.c
@@ -18,7 +18,7 @@ vector char scz;
 vector unsigned char uca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13};
 vector unsigned char ucb = {6,4,8,3,1,9,2,6,10,3,7,11,15,12,14,13};
 vector unsigned char uc_expected = {3,4,8,2,3,9,2,6,10,3,7,11,15,12,14,13};
-vector char ucz;
+vector unsigned char ucz;
 
 vector short int ssia = {9, 16, 25, 36};
 vector short int ssib = {-8, -27, -64, -125};
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c
deleted file mode 100644
index 1e690be..0000000
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7-be.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
-
-/* Expected results for Big Endian:
-     vec_packpx                     vpkpx
-     vec_ld                         lxvd2x
-     vec_lde                        lvewx
-     vec_ldl                        lxvl
-     vec_lvewx                      lvewx
-     vec_unpackh                    vupklsh
-     vec_unpackl                    vupkhsh
-     vec_andc                       xxnor
-                                    xxland
-     vec_vxor                       xxlxor
-     vec_vmsumubm                   vmsumubm
-     vec_vmulesb                    vmulesb
-     vec_vmulosb                    vmulosb
-*/
-
-/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
-/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
-/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times "lvewx" 2 } } */
-/* { dg-final { scan-assembler-times "lvxl" 1 } } */
-/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
-/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
-
-/* Source code for the test in altivec-7.h */
-#include "altivec-7.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c b/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c
deleted file mode 100644
index 38ce1536..0000000
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7-le.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/* { dg-do compile { target powerpc64le-*-* } } */
-/* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec" } */
-
-/* Expected results for Little Endian:
-     vec_packpx                     vpkpx
-     vec_vmulosb                    vmulesb
-     vec_ld                         lxv2x
-     vec_lde                        lvewx
-     vec_ldl                        lxvl
-     vec_lvewx                      lvewx
-     vec_unpackh                    vupklsh
-     vec_unpackl                    vupkhsh
-     vec_andc                       xxnor
-                                    xxland
-     vec_vxor                       xxlxor
-     vec_vmsumubm                   vmsumubm
-     vec_vmulesb                    vmulosb
-     vec_vmulosb                    vmulesb
-*/
-
-/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
-/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
-/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 36 } } */
-/* { dg-final { scan-assembler-times "lvewx" 2 } } */
-/* { dg-final { scan-assembler-times "lvxl" 1 } } */
-/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
-/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 4 } } */
-/* { dg-final { scan-assembler-times "xxland" 4 } } */
-/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
-/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */
-
-/* Source code for the test in altivec-7.h and vsx-7.h. */
-#include "altivec-7.h"
-#include "vsx-7.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
new file mode 100644
index 0000000..ba5f0eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -0,0 +1,111 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+/* Origin: Aldy Hernandez  <aldyh@redhat.com>  */
+
+#include <altivec.h>
+
+int **intp;
+int *var_int;
+unsigned int **uintp;
+vector pixel *varpixel;
+vector signed char *vecchar;
+vector signed int *vecint;
+vector signed short *vecshort;
+vector unsigned char *vecuchar;
+vector unsigned int *vecuint;
+vector bool int *vecubi;
+vector bool char *vecubci;
+vector bool short int *vecubsi;
+vector bool long long int *vecublli;
+vector unsigned short *vecushort;
+vector bool int *vecbint;
+vector float *vecfloat;
+
+int main ()
+{
+  *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]);
+  *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]);
+  *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]);
+  *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]);
+  *varpixel++ = vec_packpx(vecuint[0], vecuint[1]);
+  *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]);
+  *vecshort++ = vec_vmulesb(vecchar[0], vecchar[1]);
+  *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]);
+  *vecint++ = vec_ld(var_int[0], intp[1]);
+  *vecint++ = vec_lde(var_int[0], intp[1]);
+  *vecint++ = vec_ldl(var_int[0], intp[1]);
+  *vecint++ = vec_lvewx(var_int[0], intp[1]);
+  *vecint++ = vec_unpackh(vecshort[0]);
+  *vecint++ = vec_unpackl(vecshort[0]);
+  *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]);
+  *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]);
+  *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]);
+  *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]);
+  *vecuint++ = vec_ld(var_int[0], uintp[1]);
+  *vecuint++ = vec_lvx(var_int[0], uintp[1]);
+  *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]);
+  *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]);
+
+  *vecubi++ = vec_unpackh(vecubsi[0]);
+  *vecuint++ = vec_unpackh(varpixel[0]);
+  *vecublli++ = vec_unpackh(vecubi[0]);
+  *vecubsi++ = vec_unpackh(vecubci[0]);
+  *vecshort++ = vec_unpackh(vecchar[0]);
+
+  *vecubi++ = vec_unpackl(vecubsi[0]);
+  *vecuint++ = vec_unpackl(varpixel[0]);
+  *vecublli++ = vec_unpackl(vecubi[0]);
+  *vecubsi++ = vec_unpackl(vecubci[0]);
+  *vecshort++ = vec_unpackl(vecchar[0]);
+  
+  return 0;
+}
+
+/* Expected results:
+     vec_packpx                     vpkpx
+     vec_vmulosb                    vmulesb
+     vec_ld                         lxv2x
+     vec_lde                        lvewx
+     vec_ldl                        lxvl
+     vec_lvewx                      lvewx
+     vec_unpackh                    vupklsh
+     vec_unpackh                    vupklpx
+     vec_unpackh                    vupklsw
+     vec_unpackh                    vupklsb
+     vec_unpackl                    vupkhsh
+     vec_unpackl                    vupkhpx
+     vec_unpackl                    vupkhsw
+     vec_unpackl                    vupkhsb
+     vec_andc                       xxnor
+                                    xxland
+     vec_vxor                       xxlxor
+     vec_vmsumubm                   vmsumubm
+     vec_vmulesb                    vmulosb
+     vec_vmulosb                    vmulesb
+     vec_ld                         lvx
+*/
+
+/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
+/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
+/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 44 { target le } } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 4 { target be } } } */
+/* { dg-final { scan-assembler-times "lvewx" 2 } } */
+/* { dg-final { scan-assembler-times "lvxl" 1 } } */
+/* { dg-final { scan-assembler-times "vupklsh" 2 } } */
+/* { dg-final { scan-assembler-times "vupkhsh" 2 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 4 } } */
+/* { dg-final { scan-assembler-times "xxland" 4 } } */
+/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
+/* { dg-final { scan-assembler-times "xxlandc" 0 } } */
+/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
+/* { dg-final { scan-assembler-times "lvx" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumubm" 1 } } */
+/* { dg-final { scan-assembler-times "vupklpx" 1 } } } */
+/* { dg-final { scan-assembler-times "vupklsx" 0 } } */
+/* { dg-final { scan-assembler-times "vupklsb" 2 } } */
+/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */
+/* { dg-final { scan-assembler-times "vupkhsw" 1 } } */
+/* { dg-final { scan-assembler-times "vupkhsb" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.h b/gcc/testsuite/gcc.target/powerpc/altivec-7.h
deleted file mode 100644
index 4dedcd8..0000000
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* Origin: Aldy Hernandez  <aldyh@redhat.com>  */
-
-/* This test code is included into altivec-7-be.c and altivec-7-le.c.  
-   The two files have the tests for the number of instructions generated for
-   LE versus BE.  */
-
-#include <altivec.h>
-
-int **intp;
-int *var_int;
-unsigned int **uintp;
-vector pixel *varpixel;
-vector signed char *vecchar;
-vector signed int *vecint;
-vector signed short *vecshort;
-vector unsigned char *vecuchar;
-vector unsigned int *vecuint;
-vector unsigned short *vecushort;
-vector float *vecfloat;
-
-int main ()
-{
-  *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]);
-  *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]);
-  *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]);
-  *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]);
-  *varpixel++ = vec_packpx(vecuint[0], vecuint[1]);
-  *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]);
-  *vecshort++ = vec_vmulesb(vecchar[0], vecchar[1]);
-  *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]);
-  *vecint++ = vec_ld(var_int[0], intp[1]);
-  *vecint++ = vec_lde(var_int[0], intp[1]);
-  *vecint++ = vec_ldl(var_int[0], intp[1]);
-  *vecint++ = vec_lvewx(var_int[0], intp[1]);
-  *vecint++ = vec_unpackh(vecshort[0]);
-  *vecint++ = vec_unpackl(vecshort[0]);
-  *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]);
-  *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]);
-  *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]);
-  *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]);
-  *vecuint++ = vec_ld(var_int[0], uintp[1]);
-  *vecuint++ = vec_lvx(var_int[0], uintp[1]);
-  *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]);
-  *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]);
-
-  return 0;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-be.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-be.c
deleted file mode 100644
index 9de8baf..0000000
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1-be.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* { dg-do compile { target { powerpc64-*-* } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O0 -mno-fold-gimple -dp" } */
-/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */
-
-/* Test that a number of newly added builtin overloads are accepted
-   by the compiler.  */
-
-/* Expected results for Big Endian:
-   vec_all_eq          vcmpequd.
-   vec_all_ne          vcmpequd.
-   vec_any_eq          vcmpequd.
-   vec_any_ne          vcmpequd.
-   vec_all_gt          vcmpgtud.
-   vec_all_le          vcmpgtud.
-   vec_any_gt          vcmpgtud.
-   vec_any_lt          vcmpgtud.
-   vec_any_le          vcmpgtud.
-   vec_and             xxland
-   vec_andc            xxlandc
-   vec_cntlz           vclzd, vclzb, vclzw, vclzh
-   xvcpsgnsp  vec_cpsgn
-   vec_ctf    xvmuldp 
-   vec_cts xvcvdpsxds, vctsxs
-   vec_ctu   xvcvdpuxds, vctuxs
-   vec_div   divd, divdu | __divdi3(), __udivdi3()
-   vec_mergel vmrghb, vmrghh, xxmrghw
-   vec_mergeh  xxmrglw, vmrglh
-   vec_mul mulld | mullw, mulhwu
-   vec_nor xxlnor
-   vec_or xxlor
-   vec_packsu vpksdus
-   vec_perm vperm
-   vec_round xvrdpi
-   vec_sel xxsel
-   vec_xor xxlxor 
-   vec_rsqrt  xvrsqrtesp
-   vec_rsqrte xvrsqrtesp  */
-
-/* { dg-final { scan-assembler-times {\mvcmpequd\M\.} 4 } } */
-/* { dg-final { scan-assembler-times {\mvcmpgtud\M\.} 8 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M} 16 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M} 13 } } */
-/* { dg-final { scan-assembler-times {\mvclzb\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvclzd\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvclzw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvclzh\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxvcpsgnsp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmuldp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxvcvdpsxds\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvctsxs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvcvdpuxds\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvctuxs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvmrghb\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mvmrghh\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxmrghw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxxmrglw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvmrglh\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mxxlnor\M} 6 } } */
-/* { dg-final { scan-assembler-times {(?n)\mxxlor\M.*\mboolv4si3_internal\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mvpksdus\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxxsel\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mdivd\M} 2 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mdivdu\M} 2 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mmulld\M} 4 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mbl __divdi3\M} 2 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mbl __udivdi3\M} 2 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mmullw\M} 12 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mmulhwu\M} 4 { target ilp32 } } } */
-
-/* The source code for the test is in builtins-1.h.  */
-#include "builtins-1.h"
-
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1-le.c b/gcc/testsuite/gcc.target/powerpc/builtins-1-le.c
deleted file mode 100644
index 2dd4953..0000000
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1-le.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* { dg-do compile { target { powerpc64le-*-* } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O0 -mno-fold-gimple -dp" } */
-/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */
-
-/* Test that a number of newly added builtin overloads are accepted
-   by the compiler.  */
-
-/* Expected results for Little Endian:
-   vec_all_eq          vcmpequd.
-   vec_all_ne          vcmpequd.
-   vec_any_eq          vcmpequd.
-   vec_any_ne          vcmpequd.
-   vec_all_gt          vcmpgtud.
-   vec_all_le          vcmpgtud.
-   vec_any_gt          vcmpgtud.
-   vec_any_lt          vcmpgtud.
-   vec_any_le          vcmpgtud.
-   vec_and             xxland
-   vec_andc            xxlandc
-   vec_cntlz           vclzd, vclzb, vclzw, vclzh
-   xvcpsgnsp  vec_cpsgn
-   vec_ctf    xvmuldp 
-   vec_cts xvcvdpsxds, vctsxs
-   vec_ctu   xvcvdpuxds, vctuxs
-   vec_div   divd, divdu
-   vec_mergel vmrghb, vmrghh, xxmrghw
-   vec_mergeh  xxmrglw, vmrglh
-   vec_mul mulld
-   vec_nor xxlnor
-   vec_or xxlor
-   vec_packsu vpksdus
-   vec_perm vperm
-   vec_round xvrdpi
-   vec_sel xxsel
-   vec_xor xxlxor 
-   vec_rsqrt  xvrsqrtesp
-   vec_rsqrte xvrsqrtesp  */
-
-/* { dg-final { scan-assembler-times {\mvcmpequd\M\.} 4 } } */
-/* { dg-final { scan-assembler-times {\mvcmpgtud\M\.} 8 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M} 16 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M} 13 } } */
-/* { dg-final { scan-assembler-times {\mvclzb\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvclzd\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvclzw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvclzh\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxvcpsgnsp\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvmuldp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxvcvdpsxds\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvctsxs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxvcvdpuxds\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvctuxs\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mdivd\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mdivdu\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvmrghb\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mvmrghh\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mxxmrghw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mxxmrglw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvmrglh\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mmulld\M} 4 } } */
-/* { dg-final { scan-assembler-times {(?n)\mxxlnor\M.*\mboolccv4si3_internal1\M} 6 } } */
-/* { dg-final { scan-assembler-times {(?n)\mxxlor\M.*\mboolv4si3_internal\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mvpksdus\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvperm\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxvrdpi\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mxxsel\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M} 6 } } */
-
-/* The test code is in builtins -1.h.  */
-#include "builtins-1.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.h b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index b7d8c63..45727b9 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.h
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -1,5 +1,7 @@
-/* This test is included into builtins-1-be.c and builtins-1-le.c to test on
-   Big Endian and Little Endian machines.  */
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O0 -mno-fold-gimple -dp" } */
+/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */
 
 #include <altivec.h>
 
@@ -19,6 +21,9 @@ int main ()
   vector double db = {-2.0, -3.0};
   vector double dz = vec_and (da, db);
 
+  vector signed int si_a = {1, 2, 3, 4};
+  vector unsigned int ui_a = {1, 2, 3, 4};
+
   vector long long la = {5L, 14L};
   vector long long lb = {3L, 86L};
   vector long long lc = vec_and (la, lb);
@@ -87,6 +92,10 @@ int main ()
   vector unsigned char ca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13};
   vector unsigned char cbb = {5,4,8,3,1,9,2,6,10,3,7,11,15,12,14,13};
 
+  vector unsigned char ucba = {5,4,8,3,1,9,2,6,10,3,7,11,15,12,14,13};
+  vector unsigned char ucbb = {5,4,8,3,1,9,2,6,10,3,7,11,15,12,14,13};
+  vector unsigned char ucbc = {5,4,8,3,1,9,2,6,10,3,7,11,15,12,14,13};
+
   vector long long lv = vec_perm (la, lb, ca);
 
   vector unsigned char  ucm = vec_and (ca, cbb);
@@ -95,7 +104,6 @@ int main ()
 
   vector unsigned long long uv = vec_perm (ua, ub, ca);
 
-  vector long long lw = vec_sel (la, lb, lc);
   vector long long lx = vec_sel (la, lb, uc);
   vector long long ly = vec_sel (la, lb, ld);
 
@@ -182,6 +190,8 @@ int main ()
   vector signed char scb = vec_cntlz (sca);
   vector signed char scc = vec_mergel (sca, scb);
 
+  vector unsigned char uca = {4, 3, 9, 15, 30, 31, 0, 0,
+			      1, 117, 36, 99, 98, 97, 96, 95};
   vector unsigned char cb = vec_cntlz (ca);
 
   vector double dd = vec_xl (0, &y);
@@ -191,6 +201,10 @@ int main ()
   vector double dzz1 = vec_rsqrt (dd);
   vector double dzz2 = vec_rsqrte (dd);
 
+  vector float ff1 = vec_round (fa);
+  vector float ff2 = vec_rsqrt (fa);
+  vector float ff3 = vec_rsqrte (fa);
+
   vector double dff = vec_splat (de, 0);
   vector double dgg = vec_splat (de, 1);
   vector long long l3 = vec_splat (l2, 0);
@@ -201,7 +215,8 @@ int main ()
   vector bool long long l6 = vec_splat (ld, 1);
   vector bool long long l10 = vec_mergee (ld, ld);
   vector bool long long l11 = vec_mergeo (ld, ld);
-
+  vector bool long long l15 = vec_and (ld, ld);
+  
   vector long long l7 = vec_div (l3, l4);
   vector unsigned long long u5 = vec_div (u3, u4);
   vector long long l12 = vec_mergee (la, lb);
@@ -212,11 +227,7 @@ int main ()
   vector long long l8 = vec_mul (l3, l4);
   vector unsigned long long u6 = vec_mul (u3, u4);
 
-  vector double dh = vec_ctf (la, -2);
-  vector double di = vec_ctf (ua, 2);
   vector int sz = vec_cts (fa, 0x1F);
-  vector long long l9 = vec_cts (dh, -2);
-  vector unsigned long long u7 = vec_ctu (di, 2);
   vector unsigned int usz = vec_ctu (fa, 0x1F);
 
   vector float f1 = vec_mergee (fa, fb);
@@ -225,5 +236,132 @@ int main ()
   vector double d1 = vec_mergee (da, db);
   vector double d2 = vec_mergeo (da, db);
 
+  vector float f3 = vec_ctf (si_a, 1);
+  vector float f4 = vec_ctf (ui_a, 2);
+
+  vector bool char z_vbc2 = vec_splat (bca, 0);
+  vector signed char z_vsc1 = vec_splat (sca, 1);
+  vector unsigned char z_vuc1 = vec_splat (ucbc, 2);
+
+  vector bool int z_vbi1 = vec_splat (bia, 3);
+  vector signed int z_vsi1 = vec_splat (sia, 1);
+  vector unsigned int z_vui1 = vec_splat (uia, 2);
+
+  vector bool int z_bi2 = vec_mergee (bia, bib);
+  vector signed int z_si2 = vec_mergee (sia, sib);
+  vector unsigned int z_ui2 = vec_mergee (uia, uib);
+  
+  vector bool char z_bc2 = vec_mergeh (bca, bcb);
+  vector signed char z_sc2 = vec_mergeh (sca, scb);
+  vector bool int z_bi3 = vec_mergeh (bia, bib);
+  vector signed int z_si3 = vec_mergeh (sia, sib);
+  vector unsigned int z_ui3 = vec_mergeh (uia, uib);
+  vector bool short z_bs1 = vec_mergeh (bsa, bsb);
+
+  vector bool int z_bi4 = vec_mergeo (bia, bib);
+  vector signed int z_si4 = vec_mergeo (sia, sib);
+  vector unsigned int z_ui4 = vec_mergeo (uia, uib);
+  
+  vector pixel int z_vp1 = vec_splat (pa, 1);
+  vector bool short z_bs2 = vec_splat (bsa, 0);
+  vector short signed int z_vss1 = vec_splat (ssa, 2);
+  vector unsigned short int z_vuss1 = vec_splat (usa, 1);
+
+
   return 0;
 }
+
+/* Expected results:
+   vec_all_eq          vcmpequd.
+   vec_all_ge          vcmpgtud.
+   vec_all_ne          vcmpequd.
+   vec_any_eq          vcmpequd.
+   vec_any_ne          vcmpequd.
+   vec_all_gt          vcmpgtud.
+   vec_all_le          vcmpgtud.
+   vec_all_lt          vcmpgtud.
+   vec_any_ge          vcmpgtud.
+   vec_any_gt          vcmpgtud.
+   vec_any_lt          vcmpgtud.
+   vec_any_le          vcmpgtud.
+   vec_and             xxland
+   vec_andc            xxland
+   vec_cntlz           vclzd, vclzb, vclzw, vclzh
+   xvcpsgnsp           vec_cpsgn
+   vec_ctf             xvmuldp 
+   vec_cts             xvcvdpsxds, vctsxs
+   vec_ctu             xvcvdpuxds, vctuxs
+   vec_div             divd, divdu | __divdi3(), __udivdi3()
+   vec_mergel          vmrghb, vmrghh, xxmrghw
+   vec_mergeh          xxmrglw, vmrglh
+   vec_mul             mulld | mullw, mulhwu
+   vec_nor             xxlnor
+   vec_or              xxlor
+   vec_packsu          vpksdus
+   vec_                perm vperm
+   vec_                round xvrdpi
+   vec_sel             xxsel
+   vec_xor             xxlxor 
+   vec_rsqrt           xvrsqrtesp
+   vec_rsqrte          xvrsqrtesp
+   vec_xl              lxvd2x
+   vec_xst             stxvd2x
+   vec_splat           xxspltb, xxspltw, vsplth
+   vec_mergee          xxmrgld, vmrgow
+   vec_mergeo          xxmrghd, vmrgew  */
+
+/* { dg-final { scan-assembler-times "vcmpequd" 8 } } */
+/* { dg-final { scan-assembler-times "vcmpgtud" 16 } } */
+/* { dg-final { scan-assembler-times "xxland" 30 } } */
+/* { dg-final { scan-assembler-times "xxlandc" 13 } } */
+/* { dg-final { scan-assembler-times "vclzb" 2 } } */
+/* { dg-final { scan-assembler-times "vclzd" 2 } } */
+/* { dg-final { scan-assembler-times "vclzw" 2 } } */
+/* { dg-final { scan-assembler-times "vclzh" 2 } } */
+/* { dg-final { scan-assembler-times "xvcpsgnsp" 1 } } */
+/* { dg-final { scan-assembler-times "xvcpsgndp" 1 } } */
+/* { dg-final { scan-assembler-times "xvmuldp" 2 } } */
+/* { dg-final { scan-assembler-times "xvcvdpsxds" 0 } } */
+/* { dg-final { scan-assembler-times "vctsxs" 2 } } */
+/* { dg-final { scan-assembler-times "xvcvdpuxds" 0 } } */
+/* { dg-final { scan-assembler-times "vctuxs" 2 } } */
+
+/* { dg-final { scan-assembler-times "vmrghb" 4 { target be } } } */
+/* { dg-final { scan-assembler-times "vmrghb" 5 { target le } } } */
+/* { dg-final { scan-assembler-times "vmrghh" 8 } } */
+/* { dg-final { scan-assembler-times "xxmrghw" 8 } } */
+/* { dg-final { scan-assembler-times "xxmrglw" 8 } } */
+/* { dg-final { scan-assembler-times "vmrglh" 8 } } */
+/* { dg-final { scan-assembler-times "xxlnor" 6 } } */
+/* { dg-final { scan-assembler-times "xxlor" 11 { target { ilp32 } } } } */
+/* { dg-final { scan-assembler-times "xxlor" 7  { target { lp64 } } } } */
+/* { dg-final { scan-assembler-times "vpksdus" 2 } } */
+/* { dg-final { scan-assembler-times "vperm" 4 } } */
+/* { dg-final { scan-assembler-times "xvrdpi" 2 } } */
+/* { dg-final { scan-assembler-times "xxsel" 10 } } */
+/* { dg-final { scan-assembler-times "xxlxor" 6 } } */
+/* { dg-final { scan-assembler-times "divd" 8  { target lp64 } } } */
+/* { dg-final { scan-assembler-times "divdu" 2  { target lp64 } } } */
+/* { dg-final { scan-assembler-times "mulld" 4  { target lp64 } } } */
+/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "bl __udivdi3" 3  { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "mullw" 12  { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "mulhwu" 4  { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "xxmrgld" 0 } } */
+/* { dg-final { scan-assembler-times "xxmrghd" 0 } } */
+/* { dg-final { scan-assembler-times "xvrsqrtesp" 2 } } */
+/* { dg-final { scan-assembler-times "xvrsqrtedp" 2 } } */
+/* { dg-final { scan-assembler-times "xxspltd" 8 } } */
+/* { dg-final { scan-assembler-times "vcfsx" 2 } } */
+/* { dg-final { scan-assembler-times "vcfux" 2 } } */
+/* { dg-final { scan-assembler-times "vspltb" 6 } } */
+/* { dg-final { scan-assembler-times "vspltw" 0 } } */
+/* { dg-final { scan-assembler-times "vmrgow" 8 } } */
+/* { dg-final { scan-assembler-times "vmrglb" 5 { target le } } } */
+/* { dg-final { scan-assembler-times "vmrglb" 6 { target be } } } */
+/* { dg-final { scan-assembler-times "vmrgew" 8 } } */
+/* { dg-final { scan-assembler-times "vsplth" 8 } } */
+/* { dg-final { scan-assembler-times "vcmpequd." 8 } } */
+/* { dg-final { scan-assembler-times "vcmpgtud." 16 } } */
+/* { dg-final { scan-assembler-times "vrfin" 2 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
index 325796c..0231a1f 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
@@ -179,7 +179,7 @@ int main()
 	vector long long int vec_ll_int_expected, vec_ll_int_result;
 	vector long long unsigned int vec_ll_uns_int0, vec_ll_uns_int1;
 	vector long long unsigned int vec_ll_uns_int_expected, vec_ll_uns_int_result;
-	vector float  vec_flt, vec_flt_result, vec_flt_expected;
+	vector float  vec_flt0, vec_flt1, vec_flt_result, vec_flt_expected;
 	vector double vec_dble0, vec_dble1, vec_dble_result, vec_dble_expected;
 
 	vec_int = (vector signed int){ -1, 3, -5, 1234567 };
@@ -188,7 +188,7 @@ int main()
 	vec_unint = (vector unsigned int){ 9, 11, 15, 2468013579 };
 	vec_ll_uns_int0 = (vector unsigned long long int){ 102, 9753108642 };
 	vec_ll_uns_int1 = (vector unsigned long long int){ 23, 29 };
-	vec_flt = (vector float){ -21., 3.5, -53., 78. };
+	vec_flt0 = (vector float){ -21., 3.5, -53., 78. };
 	vec_dble0 = (vector double){ 34.0, 97.0 };
 	vec_dble1 = (vector double){ 214.0, -5.5 };
 
@@ -202,7 +202,7 @@ int main()
 	test_result_dp(vec_dble_result, vec_dble_expected);
 
 	vec_dble_expected = (vector double){-21.000000, -53.000000};
-	vec_dble_result = vec_doublee (vec_flt);
+	vec_dble_result = vec_doublee (vec_flt0);
 	test_result_dp(vec_dble_result, vec_dble_expected);
 
 
@@ -216,7 +216,7 @@ int main()
 	test_result_dp(vec_dble_result, vec_dble_expected);
 
 	vec_dble_expected = (vector double){3.500000, 78.000000};
-	vec_dble_result = vec_doubleo (vec_flt);
+	vec_dble_result = vec_doubleo (vec_flt0);
 	test_result_dp(vec_dble_result, vec_dble_expected);
 
 
@@ -230,7 +230,7 @@ int main()
 	test_result_dp(vec_dble_result, vec_dble_expected);
 
 	vec_dble_expected = (vector double){-53.000000, 78.000000};
-	vec_dble_result = vec_doublel (vec_flt);
+	vec_dble_result = vec_doublel (vec_flt0);
 	test_result_dp(vec_dble_result, vec_dble_expected);
 
 
@@ -244,7 +244,7 @@ int main()
 	test_result_dp(vec_dble_result, vec_dble_expected);
 
 	vec_dble_expected = (vector double){-21.000000, 3.500000};
-	vec_dble_result = vec_doubleh (vec_flt);
+	vec_dble_result = vec_doubleh (vec_flt0);
 	test_result_dp(vec_dble_result, vec_dble_expected);
 
 	/* conversion of integer vector to single precision float vector */
@@ -283,9 +283,9 @@ int main()
 	test_result_sp(ODD, vec_flt_result, vec_flt_expected);
 
 	/* Convert single precision float to int */
-	vec_flt = (vector float){-14.30, 34.00, 22.00, 97.00};
+	vec_flt0 = (vector float){-14.30, 34.00, 22.00, 97.00};
 	vec_int_expected = (vector signed int){-14, 34, 22, 97};
-	vec_int_result = vec_signed (vec_flt);
+	vec_int_result = vec_signed (vec_flt0);
 	test_int_result (ALL, vec_int_result, vec_int_expected);
 
 	/* Convert double precision float to long long int */
@@ -306,6 +306,13 @@ int main()
 	vec_int_result = vec_signedo (vec_dble0);
 	test_int_result (ODD, vec_int_result, vec_int_expected);
 
+	/* Convert single precision float to  unsigned int */
+	vec_flt0 = (vector float){124.930, 8134.49, 23.3, 45.4};
+	vec_uns_int_expected = (vector unsigned int){124, 8134, 23, 45};
+	vec_uns_int_result = vec_unsigned (vec_flt0);
+	test_unsigned_int_result (ALL, vec_uns_int_result,
+				  vec_uns_int_expected);
+
 	/* Convert double precision float to long long unsigned int */
 	vec_dble0 = (vector double){124.930, 8134.49};
 	vec_ll_uns_int_expected = (vector long long unsigned int){124, 8134};
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
index 0288b80..f0edd12 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
@@ -1,7 +1,6 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-O2 -mvsx -mcpu=power6" } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power6" } } */
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
 
 #include <altivec.h>
 
@@ -83,6 +82,20 @@ test_sll_vui_vui_vuc (vector unsigned int x, vector unsigned char y)
 	return vec_sll (x, y);
 }
 
+vector signed int long long
+test_sll_vsill_vsill_vuc (vector signed long long int x,
+			  vector unsigned char y)
+{
+	return vec_sll (x, y);
+}
+
+vector unsigned int long long
+test_sll_vuill_vuill_vuc (vector unsigned long long int x,
+			  vector unsigned char y)
+{
+	return vec_sll (x, y);
+}
+
 vector bool long long
 test_sll_vbll_vbll_vuc (vector bool long long x,
 			vector unsigned char y)
@@ -310,18 +323,46 @@ test_cmpb_float (vector float x, vector float y)
      test_nabs_int             1 vspltisw, 1 vsubuwm, 1 vminsw
      test_nabs_float           1 xvnabssp
      test_nabs_double          1 xvnabsdp
-     test_vsll_slo_vsll_vsc    1 vslo
-     test_vsll_slo_vsll_vuc    1 vslo
-     test_vull_slo_vsll_vsc    1 vslo
-     test_vull_slo_vsll_vuc    1 vslo
-     test_vsc_mulo_vsc_vsc     1 xxsldwi
-     test_vuc_mulo_vuc_vuc     1 xxsldwi
-     test_vssi_mulo_vssi_vssi  1 xxsldwi
-     test_vusi_mulo_vusi_vusi  1 xxsldwi
-     test_vsi_mulo_vsi_vsi     1 xxsldwi
-     test_vui_mulo_vui_vui     1 xxsldwi
-     test_vsl_mulo_vsl_vsl     1 xxsldwi
-     test_vul_mulo_vul_vul     1 xxsldwi
+     test_sll_vsc_vsc_vsuc     1 vsl
+     test_sll_vuc_vuc_vuc      1 vsl
+     test_sll_vsi_vsi_vuc      1 vsl
+     test_sll_vui_vui_vuc      1 vsl
+     test_sll_vsill_vsill_vuc  1 vsl
+     test_sll_vuill_vuill_vuc  1 vsl
+     test_sll_vbll_vbll_vuc    1 vsl
+     test_sll_vbll_vbll_vull   1 vsl
+     test_sll_vbll_vbll_vus    1 vsl
+     test_sll_vp_vp_vuc        1 vsl
+     test_sll_vssi_vssi_vuc    1 vsl
+     test_sll_vusi_vusi_vuc    1 vsl
+     test_slo_vsc_vsc_vsc      1 vslo
+     test_slo_vsc_vsc_vuc      1 vslo
+     test_slo_vuc_vuc_vsc      1 vslo
+     test_slo_vuc_vuc_vuc      1 vslo
+     test_slo_vsi_vsi_vsc      1 vslo
+     test_slo_vsi_vsi_vuc      1 vslo
+     test_slo_vui_vui_vsc      1 vslo
+     test_slo_vui_vui_vuc      1 vslo
+     test_slo_vsll_slo_vsll_vsc 1 vslo
+     test_slo_vsll_slo_vsll_vuc 1 vslo
+     test_slo_vull_slo_vull_vsc 1 vslo
+     test_slo_vull_slo_vull_vuc 1 vslo
+     test_slo_vp_vp_vsc        1 vslo
+     test_slo_vp_vp_vuc        1 vslo
+     test_slo_vssi_vssi_vsc    1 vslo
+     test_slo_vssi_vssi_vuc    1 vslo
+     test_slo_vusi_vusi_vsc    1 vslo
+     test_slo_vusi_vusi_vuc    1 vslo
+     test_slo_vf_vf_vsc        1 vslo
+     test_slo_vf_vf_vuc        1 vslo
+     test_vsc_sldw_vsc_vsc     1 xxsldwi
+     test_vuc_sldw_vuc_vuc     1 xxsldwi
+     test_vssi_sldw_vssi_vssi  1 xxsldwi
+     test_vusi_sldw_vusi_vusi  1 xxsldwi
+     test_vsi_sldw_vsi_vsi     1 xxsldwi
+     test_vui_sldw_vui_vui     1 xxsldwi
+     test_vsl_sldw_vsl_vsl     1 xxsldwi
+     test_vul_sldw_vul_vul     1 xxsldwi
      test_cmpb_float           1 vcmpbfp */
 
 /* { dg-final { scan-assembler-times "vcmpequb" 1 } } */
@@ -340,3 +381,6 @@ test_cmpb_float (vector float x, vector float y)
 /* { dg-final { scan-assembler-times "vslo"    20 } } */
 /* { dg-final { scan-assembler-times "xxsldwi"  8 } } */
 /* { dg-final { scan-assembler-times "vcmpbfp"  1 } } */
+/* { dg-final { scan-assembler-times "vsl"     68 { target le } } } */
+/* { dg-final { scan-assembler-times "vsl"     68 { target { be && ilp32 } } } } */
+/* { dg-final { scan-assembler-times "vsl"     82 { target { be && lp64  } } } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c
index a4a1939..70fe528 100644
--- a/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/p9-xxbr-2.c
@@ -26,6 +26,12 @@ rev_long_long (vector long long a)
   return vec_revb (a);		/* XXBRD.  */
 }
 
+vector bool long long
+rev_bool_long_long (vector bool long long a)
+{
+  return vec_revb (a);		/* XXBRD.  */
+}
+
 vector unsigned long long
 rev_ulong_ulong (vector unsigned long long a)
 {
@@ -44,5 +50,5 @@ rev_uint128 (vector __uint128_t a)
   return vec_revb (a);		/* XXBRQ.  */
 }
 
-/* { dg-final { scan-assembler-times "xxbrd" 4 } } */
+/* { dg-final { scan-assembler-times "xxbrd" 5 } } */
 /* { dg-final { scan-assembler-times "xxbrq" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c b/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c
deleted file mode 100644
index 2df9fca..0000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-7-be.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile { target powerpc*-*-* } } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx" } */
-
-/* This is an extension of altivec-7-be.c, with vsx target features included. */
-
-/* Expected results for Big Endian:
-(from altivec-7.h)
-     vec_packpx                     vpkpx
-     vec_ld                         lxvd2x or lxv
-     vec_lde                        lvewx
-     vec_ldl                        lxvl
-     vec_lvewx                      lvewx
-     vec_andc                       xxnor
-                                    xxland
-     vec_vxor                       xxlxor
-     vec_vmsumubm                   vmsumubm
-     vec_vmulesb                    vmulesb
-     vec_vmulosb                    vmulosb
-(from vsx-7.h)
-     vec_unpackl                    vupkhsh
-     vec_unpackh                    vupklsh
-*/
-
-/* { dg-final { scan-assembler-times "vpkpx" 2 } } */
-/* { dg-final { scan-assembler-times "vmulesb" 1 } } */
-/* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-
-// For LE platforms P9 and later, we generate the lxv insn instead of lxvd2x.
-/* { dg-final { scan-assembler-times {\mlxvd2x\M}  0  { target { { powerpc64*le-*-* } && { p9vector_hw } } } } } */
-/* { dg-final { scan-assembler-times {\mlxv\M}    36  { target { { powerpc64*le-*-* } && { p9vector_hw } } } } } */
-// For LE platforms < P9.
-/* { dg-final { scan-assembler-times {\mlxvd2x\M}  36  { target { { powerpc64*le-*-* } && { ! p9vector_hw } } } } } */
-// For BE platforms we generate 6 lxvd2x insns.
-/* { dg-final { scan-assembler-times {\mlxvd2x\M}  6  { target { { ! powerpc64*le-*-* } && { ! p9vector_hw } } } } } */
-
-/* { dg-final { scan-assembler-times "lvewx" 2 } } */
-/* { dg-final { scan-assembler-times "lvxl" 1 } } */
-/* { dg-final { scan-assembler-times "vupklsh" 1 } } */
-/* { dg-final { scan-assembler-times "vupkhsh" 1 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 4 } } */
-/* { dg-final { scan-assembler-times "xxland" 4 } } */
-/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
-/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */
-
-/* Source code for the 'altivec' test in altivec-7.h */
-/* Source code for the 'vsx' required tests in vsx-7.h */
-
-#include "altivec-7.h"
-#include "vsx-7.h"
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-7.c
new file mode 100644
index 0000000..94cb69e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-7.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-mvsx" } */
+
+#include <altivec.h>
+
+vector float *vecfloat;
+vector double *vecdouble;
+
+int main2 ()
+{
+
+  *vecdouble++ = vec_unpackl(vecfloat[0]);
+  *vecdouble++ = vec_unpackh(vecfloat[0]);
+
+  return 0;
+}
+
+/* Expected results:
+     vec_unpackl                    vupkhsh
+     vec_unpackh                    vupklsh
+*/
+
+/* { dg-final { scan-assembler-times "vupkhpx" 1 } } */
+/* { dg-final { scan-assembler-times "vupklpx" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-7.h b/gcc/testsuite/gcc.target/powerpc/vsx-7.h
deleted file mode 100644
index fe55472..0000000
--- a/gcc/testsuite/gcc.target/powerpc/vsx-7.h
+++ /dev/null
@@ -1,18 +0,0 @@
-
-/* This test code is included into vsx-7-be.c.
- * this is meant to supplement code in altivec-7.h.  */
-
-#include <altivec.h>
-
-
-vector float *vecfloat;
-vector double *vecdouble;
-
-int main2 ()
-{
-
-  *vecdouble++ = vec_unpackl(vecfloat[0]);
-  *vecdouble++ = vec_unpackh(vecfloat[0]);
-
-  return 0;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
index 8a85775..03e3919 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c
@@ -8,17 +8,22 @@
    supported with various options.  */
 
 #include <altivec.h>
-
-double extract_df_0_reg (vector double p) { return vec_extract (p, 0); }
-double extract_df_1_reg (vector double p) { return vec_extract (p, 1); }
+int c0 = 0;
+int c1 = 1;
+int c3 = 3;
+int c7 = 7;
+int c15 = 15;
+
+double extract_df_0_reg (vector double p) { return vec_extract (p, c0); }
+double extract_df_1_reg (vector double p) { return vec_extract (p, c1); }
 double extract_df_n_reg (vector double p, int n) { return vec_extract (p, n); }
 
-double extract_df_0_mem (vector double *p) { return vec_extract (*p, 0); }
-double extract_df_1_mem (vector double *p) { return vec_extract (*p, 1); }
+double extract_df_0_mem (vector double *p) { return vec_extract (*p, c0); }
+double extract_df_1_mem (vector double *p) { return vec_extract (*p, c1); }
 double extract_df_n_mem (vector double *p, int n) { return vec_extract (*p, n); }
 
-vector double insert_df_0 (vector double p, double x) { return vec_insert (x, p, 0); }
-vector double insert_df_1 (vector double p, double x) { return vec_insert (x, p, 1); }
+vector double insert_df_0 (vector double p, double x) { return vec_insert (x, p, c0); }
+vector double insert_df_1 (vector double p, double x) { return vec_insert (x, p, c1); }
 vector double insert_df_n (vector double p, double x, int n) { return vec_insert (x, p, n); }
 
 vector double splat_df_reg (double x) { return vec_splats (x); }
@@ -30,122 +35,167 @@ vector double splat_df_mem (double *x) { return vec_splats (*x); }
 #define ll long long
 #endif
 
-ll extract_di_0_reg (vector ll p) { return vec_extract (p, 0); }
-ll extract_di_1_reg (vector ll p) { return vec_extract (p, 1); }
+ll extract_di_0_reg (vector ll p) { return vec_extract (p, c0); }
+ll extract_di_1_reg (vector ll p) { return vec_extract (p, c1); }
 ll extract_di_n_reg (vector ll p, int n) { return vec_extract (p, n); }
 
-ll extract_di_0_mem (vector ll *p) { return vec_extract (*p, 0); }
-ll extract_di_1_mem (vector ll *p) { return vec_extract (*p, 1); }
+ll extract_di_0_mem (vector ll *p) { return vec_extract (*p, c0); }
+ll extract_di_1_mem (vector ll *p) { return vec_extract (*p, c1); }
 ll extract_di_n_mem (vector ll *p, int n) { return vec_extract (*p, n); }
 
-vector ll insert_di_0 (vector ll p, ll x) { return vec_insert (x, p, 0); }
-vector ll insert_di_1 (vector ll p, ll x) { return vec_insert (x, p, 1); }
+vector ll insert_di_0 (vector ll p, ll x) { return vec_insert (x, p, c0); }
+vector ll insert_di_1 (vector ll p, ll x) { return vec_insert (x, p, c1); }
 vector ll insert_di_n (vector ll p, ll x, int n) { return vec_insert (x, p, n); }
+vector ll insert_di_0_v2 (vector ll int p, ll int x) { return vec_insert (x, p, c0); }
+vector unsigned ll insert_di_0_v3 (vector unsigned ll int p, unsigned ll int x) { return vec_insert (x, p, c0); }
 
 vector ll splat_di_reg (ll x) { return vec_splats (x); }
 vector ll splat_di_mem (ll *x) { return vec_splats (*x); }
 
-float extract_sf_0_reg (vector float p) { return vec_extract (p, 0); }
-float extract_sf_3_reg (vector float p) { return vec_extract (p, 3); }
+float extract_sf_0_reg (vector float p) { return vec_extract (p, c0); }
+float extract_sf_3_reg (vector float p) { return vec_extract (p, c3); }
 float extract_sf_n_reg (vector float p, int n) { return vec_extract (p, n); }
 
-float extract_sf_0_mem (vector float *p) { return vec_extract (*p, 0); }
-float extract_sf_3_mem (vector float *p) { return vec_extract (*p, 3); }
+float extract_sf_0_mem (vector float *p) { return vec_extract (*p, c0); }
+float extract_sf_3_mem (vector float *p) { return vec_extract (*p, c3); }
 float extract_sf_n_mem (vector float *p, int n) { return vec_extract (*p, n); }
 
-vector float insert_sf_0 (vector float p, float x) { return vec_insert (x, p, 0); }
-vector float insert_sf_3 (vector float p, float x) { return vec_insert (x, p, 3); }
+vector float insert_sf_0 (vector float p, float x) { return vec_insert (x, p, c0); }
+vector float insert_sf_3 (vector float p, float x) { return vec_insert (x, p, c3); }
 vector float insert_sf_n (vector float p, float x, int n) { return vec_insert (x, p, n); }
 
 vector float splat_sf_reg (float x) { return vec_splats (x); }
 vector float splat_sf_mem (float *x) { return vec_splats (*x); }
 
-int extract_si_0_reg (vector int p) { return vec_extract (p, 0); }
-int extract_si_3_reg (vector int p) { return vec_extract (p, 3); }
+int extract_si_0_reg (vector int p) { return vec_extract (p, c0); }
+int extract_si_3_reg (vector int p) { return vec_extract (p, c3); }
 int extract_si_n_reg (vector int p, int n) { return vec_extract (p, n); }
 
-int extract_si_0_mem (vector int *p) { return vec_extract (*p, 0); }
-int extract_si_3_mem (vector int *p) { return vec_extract (*p, 3); }
+int extract_si_0_mem (vector int *p) { return vec_extract (*p, c0); }
+int extract_si_3_mem (vector int *p) { return vec_extract (*p, c3); }
 int extract_si_n_mem (vector int *p, int n) { return vec_extract (*p, n); }
 
-vector int insert_si_0 (vector int p, int x) { return vec_insert (x, p, 0); }
-vector int insert_si_3 (vector int p, int x) { return vec_insert (x, p, 3); }
+vector int insert_si_0 (vector int p, int x) { return vec_insert (x, p, c0); }
+vector int insert_si_3 (vector int p, int x) { return vec_insert (x, p, c3); }
 vector int insert_si_n (vector int p, int x, int n) { return vec_insert (x, p, n); }
 
 vector int splat_si_reg (int x) { return vec_splats (x); }
 vector int splat_si_mem (int *x) { return vec_splats (*x); }
 
-unsigned int extract_usi_0_reg (vector unsigned int p) { return vec_extract (p, 0); }
-unsigned int extract_usi_3_reg (vector unsigned int p) { return vec_extract (p, 3); }
+unsigned int extract_usi_0_reg (vector unsigned int p) { return vec_extract (p, c0); }
+unsigned int extract_usi_3_reg (vector unsigned int p) { return vec_extract (p, c3); }
 unsigned int extract_usi_n_reg (vector unsigned int p, int n) { return vec_extract (p, n); }
 
-unsigned int extract_usi_0_mem (vector unsigned int *p) { return vec_extract (*p, 0); }
-unsigned int extract_usi_3_mem (vector unsigned int *p) { return vec_extract (*p, 3); }
+unsigned int extract_usi_0_mem (vector unsigned int *p) { return vec_extract (*p, c0); }
+unsigned int extract_usi_3_mem (vector unsigned int *p) { return vec_extract (*p, c3); }
 unsigned int extract_usi_n_mem (vector unsigned int *p, int n) { return vec_extract (*p, n); }
 
-vector unsigned int insert_usi_0 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, 0); }
-vector unsigned int insert_usi_3 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, 3); }
+vector unsigned int insert_usi_0 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, c0); }
+vector unsigned int insert_usi_3 (vector unsigned int p, unsigned int x) { return vec_insert (x, p, c3); }
 vector unsigned int insert_usi_n (vector unsigned int p, unsigned int x, int n) { return vec_insert (x, p, n); }
 
 vector unsigned int splat_usi_reg (unsigned int x) { return vec_splats (x); }
 vector unsigned int splat_usi_mem (unsigned int *x) { return vec_splats (*x); }
 
-short extract_hi_0_reg (vector short p) { return vec_extract (p, 0); }
-short extract_hi_7_reg (vector short p) { return vec_extract (p, 7); }
+short extract_hi_0_reg (vector short p) { return vec_extract (p, c0); }
+short extract_hi_7_reg (vector short p) { return vec_extract (p, c7); }
 short extract_hi_n_reg (vector short p, int n) { return vec_extract (p, n); }
 
-short extract_hi_0_mem (vector short *p) { return vec_extract (*p, 0); }
-short extract_hi_7_mem (vector short *p) { return vec_extract (*p, 7); }
+short extract_hi_0_mem (vector short *p) { return vec_extract (*p, c0); }
+short extract_hi_7_mem (vector short *p) { return vec_extract (*p, c7); }
 short extract_hi_n_mem (vector short *p, int n) { return vec_extract (*p, n); }
 
-vector short insert_hi_0 (vector short p, short x) { return vec_insert (x, p, 0); }
-vector short insert_hi_7 (vector short p, short x) { return vec_insert (x, p, 7); }
+vector short insert_hi_0 (vector short p, short x) { return vec_insert (x, p, c0); }
+vector short insert_hi_7 (vector short p, short x) { return vec_insert (x, p, c7); }
 vector short insert_hi_n (vector short p, short x, int n) { return vec_insert (x, p, n); }
 
 vector short splat_hi_reg (short x) { return vec_splats (x); }
 vector short splat_hi_mem (short *x) { return vec_splats (*x); }
 
-unsigned short extract_uhi_0_reg (vector unsigned short p) { return vec_extract (p, 0); }
-unsigned short extract_uhi_7_reg (vector unsigned short p) { return vec_extract (p, 7); }
+unsigned short extract_uhi_0_reg (vector unsigned short p) { return vec_extract (p, c0); }
+unsigned short extract_uhi_7_reg (vector unsigned short p) { return vec_extract (p, c7); }
 unsigned short extract_uhi_n_reg (vector unsigned short p, int n) { return vec_extract (p, n); }
 
-unsigned short extract_uhi_0_mem (vector unsigned short *p) { return vec_extract (*p, 0); }
-unsigned short extract_uhi_7_mem (vector unsigned short *p) { return vec_extract (*p, 7); }
+unsigned short extract_uhi_0_mem (vector unsigned short *p) { return vec_extract (*p, c0); }
+unsigned short extract_uhi_7_mem (vector unsigned short *p) { return vec_extract (*p, c7); }
 unsigned short extract_uhi_n_mem (vector unsigned short *p, int n) { return vec_extract (*p, n); }
 
-vector unsigned short insert_uhi_0 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, 0); }
-vector unsigned short insert_uhi_7 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, 7); }
+vector unsigned short insert_uhi_0 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, c0); }
+vector unsigned short insert_uhi_7 (vector unsigned short p, unsigned short x) { return vec_insert (x, p, c7); }
 vector unsigned short insert_uhi_n (vector unsigned short p, unsigned short x, int n) { return vec_insert (x, p, n); }
 
 vector unsigned short splat_uhi_reg (unsigned short x) { return vec_splats (x); }
 vector unsigned short splat_uhi_mem (unsigned short *x) { return vec_splats (*x); }
 
-signed char extract_qi_0_reg (vector signed char p) { return vec_extract (p, 0); }
-signed char extract_qi_1_reg5 (vector signed char p) { return vec_extract (p, 15); }
+signed char extract_qi_0_reg (vector signed char p) { return vec_extract (p, c0); }
+unsigned char extract_uqi_0_reg (vector unsigned char p) { return vec_extract (p, c0); }
+signed char extract_qi_1_reg5 (vector signed char p) { return vec_extract (p, c15); }
 signed char extract_qi_n_reg (vector signed char p, int n) { return vec_extract (p, n); }
 
-signed char extract_qi_0_mem (vector signed char *p) { return vec_extract (*p, 0); }
-signed char extract_qi_1_mem5 (vector signed char *p) { return vec_extract (*p, 15); }
+signed char extract_qi_0_mem (vector signed char *p) { return vec_extract (*p, c0); }
+signed char extract_qi_1_mem5 (vector signed char *p) { return vec_extract (*p, c15); }
 signed char extract_qi_n_mem (vector signed char *p, int n) { return vec_extract (*p, n); }
 
-vector signed char insert_qi_0 (vector signed char p, signed char x) { return vec_insert (x, p, 0); }
-vector signed char insert_qi_15 (vector signed char p, signed char x) { return vec_insert (x, p, 15); }
+vector signed char insert_qi_0 (vector signed char p, signed char x) { return vec_insert (x, p, c0); }
+vector signed char insert_qi_15 (vector signed char p, signed char x) { return vec_insert (x, p, c15); }
 vector signed char insert_qi_n (vector signed char p, signed char x, int n) { return vec_insert (x, p, n); }
 
 vector signed char splat_qi_reg (signed char x) { return vec_splats (x); }
 vector signed char splat_qi_mem (signed char *x) { return vec_splats (*x); }
 
-unsigned char extract_uqi_0_reg (vector unsigned char p) { return vec_extract (p, 0); }
-unsigned char extract_uqi_1_reg5 (vector unsigned char p) { return vec_extract (p, 15); }
+unsigned char extract_uqi_1_reg5 (vector unsigned char p) { return vec_extract (p, c15); }
 unsigned char extract_uqi_n_reg (vector unsigned char p, int n) { return vec_extract (p, n); }
 
-unsigned char extract_uqi_0_mem (vector unsigned char *p) { return vec_extract (*p, 0); }
-unsigned char extract_uqi_1_mem5 (vector unsigned char *p) { return vec_extract (*p, 15); }
+unsigned char extract_uqi_0_mem (vector unsigned char *p) { return vec_extract (*p, c0); }
+unsigned char extract_uqi_1_mem5 (vector unsigned char *p) { return vec_extract (*p, c15); }
 unsigned char extract_uqi_n_mem (vector unsigned char *p, int n) { return vec_extract (*p, n); }
 
-vector unsigned char insert_uqi_0 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, 0); }
-vector unsigned char insert_uqi_15 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, 15); }
+vector unsigned char insert_uqi_0 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, c0); }
+vector unsigned char insert_uqi_15 (vector unsigned char p, unsigned char x) { return vec_insert (x, p, c15); }
 vector unsigned char insert_uqi_n (vector unsigned char p, unsigned char x, int n) { return vec_insert (x, p, n); }
 
 vector unsigned char splat_uqi_reg (unsigned char x) { return vec_splats (x); }
 vector unsigned char splat_uqi_mem (unsigned char *x) { return vec_splats (*x); }
+
+vector signed char splat_sc_s8 () { return vec_splat_s8 (2); }
+vector unsigned char splat_uc_u8 () { return vec_splat_u8 (3); }
+
+vector signed short int splat_ssi_s16() { return vec_splat_s16 (4); }
+vector unsigned short int splat_usi_s16() { return vec_splat_u16 (5); }
+
+vector signed int splat_si_s32() { return vec_splat_s32 (6); }
+vector unsigned int splat_ui_u32() { return vec_splat_u32 (7); }
+
+vector signed long long splat_sll (signed long long x)
+  { return vec_splats (x); }
+
+vector unsigned long long splat_uc (unsigned long long x)
+  { return vec_splats (x); }
+
+#ifdef __SIZEOF_INT128__
+/* Note, int128 not supported on 32-bit platforms.  */
+vector signed __int128 splat_int128 (signed __int128 x) { return vec_splats (x); }
+vector unsigned __int128 splat_uint128 (unsigned __int128 x) { return vec_splats (x); }
+#endif
+
+/* Expected results:
+   vec_extract                       rldic
+   vec_insert                        rldicr
+   vec_splats                        xxspltd detected as xxpermdi
+   vec_splat_s8                      vspltisb
+   vec_splat_u8                      vspltisb
+   vec_splat_s16                     vspltish
+   vec_splat_u16                     vspltish
+   vec_splat_s32                     vspltisw
+   vec_splat_u32                     vspltisw
+   return 128 vec_splats             vspltisw
+ */
+
+/* { dg-final { scan-assembler-times {\mrldic\M} 0  { target { be && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mrldic\M} 64 { target { be && lp64 } } } } */
+/* { dg-final { scan-assembler-times {\mrldic\M} 64 { target le } } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 4 { target be } } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 6 { target le } } } */
+/* { dg-final { scan-assembler-times "vspltisb" 2 } } */
+/* { dg-final { scan-assembler-times "vspltish" 2 } } */
+/* { dg-final { scan-assembler-times "vspltisw" 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
index 3e2068b..4570dc3 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-5.c
@@ -121,8 +121,14 @@ vnearbyint_f (vector float arg)
   return vec_nearbyint (arg);
 }
 
+static vector float
+vrint_f (vector float arg)
+{
+  return vec_rint (arg);
+}
+
 static vector double
-vrint (vector double arg)
+vrint_d (vector double arg)
 {
   return vec_rint (arg);
 }
@@ -159,9 +165,9 @@ static struct
   { {  1.0,  2.0 },	{  1.1,  1.7 },		vnearbyint_d,	"vnearbyint_d" },
   { { -1.0, -2.0 },	{ -1.1, -1.7 },		vnearbyint_d,	"vnearbyint_d" },
   { { -2.0,  2.0 },	{ -1.5,  1.5 },		vnearbyint_d,	"vnearbyint_d" },
-  { {  1.0,  2.0 },	{  1.1,  1.7 },		vrint,		"vrint" },
-  { { -1.0, -2.0 },	{ -1.1, -1.7 },		vrint,		"vrint" },
-  { { -2.0,  2.0 },	{ -1.5,  1.5 },		vrint,		"vrint" },
+  { {  1.0,  2.0 },	{  1.1,  1.7 },		vrint_d,	"vrint_d" },
+  { { -1.0, -2.0 },	{ -1.1, -1.7 },		vrint_d,	"vrint_d" },
+  { { -2.0,  2.0 },	{ -1.5,  1.5 },		vrint_d,	"vrint_d" },
 
   { {  2.0,  4.0 },	{  4.0, 16.0 },		vsqrt_d,	"vsqrt_d" },
 };
@@ -213,6 +219,9 @@ static struct
   { {  1.0,  2.0, -3.0, 3.0 },	{  1.1,  1.7, -3.1, 3.1 },	vnearbyint_f,	"vnearbyint_f" },
   { { -1.0, -2.0, -3.0, 3.0 },	{ -1.1, -1.7, -2.9, 2.9 },	vnearbyint_f,	"vnearbyint_f" },
   { { -2.0,  2.0, -3.0, 3.0 },	{ -1.5,  1.5, -2.55, 3.49 },	vnearbyint_f,	"vnearbyint_f" },
+  { {  10.0,  18.0, 30.0, 40.0 }, {  10.1,  17.7, 30.0, 40.01 }, vrint_f,	"vrint_f" },
+  { { -11.0, -18.0, -30.0, -40.0 }, { -11.1, -17.7, -30.0, -40.01 }, vrint_f,	"vrint_f" },
+  
   { {  2.0,  4.0 },	{  4.0, 16.0 },		vsqrt_f,	"vsqrt_f" },
 };