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| author | Maxim Kuvyrkov <maxim@codesourcery.com> | 2010-05-05 17:11:26 +0000 |
|---|---|---|
| committer | Maxim Kuvyrkov <mkuvyrkov@gcc.gnu.org> | 2010-05-05 17:11:26 +0000 |
| commit | fa6aeae1ad6baf1e8e201508c9db8b4df00024df (patch) | |
| tree | 83a3c8c6d34c73d84fc62f680b248da28128099c /gcc | |
| parent | 6d729f282c059987f966fc3d9c98eb74e2d92839 (diff) | |
| download | gcc-fa6aeae1ad6baf1e8e201508c9db8b4df00024df.zip gcc-fa6aeae1ad6baf1e8e201508c9db8b4df00024df.tar.gz gcc-fa6aeae1ad6baf1e8e201508c9db8b4df00024df.tar.bz2 | |
* doc/invoke.texi (-mfix-cortex-m3-ldrd): Move from ARC section to ARM.
From-SVN: r159073
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 14 |
2 files changed, 11 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 26ef33b..e2c1081 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2010-05-05 Maxim Kuvyrkov <maxim@codesourcery.com> + + * doc/invoke.texi (-mfix-cortex-m3-ldrd): Move from ARC section to ARM. + 2010-05-05 Jason Merrill <jason@redhat.com> PR c++/43787 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 237f894..6a60fbb3 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -9742,13 +9742,6 @@ Put functions, data, and readonly data in @var{text-section}, by default. This can be overridden with the @code{section} attribute. @xref{Variable Attributes}. -@item -mfix-cortex-m3-ldrd -@opindex mfix-cortex-m3-ldrd -Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions -with overlapping destination and base registers are used. This option avoids -generating these instructions. This option is enabled by default when -@option{-mcpu=cortex-m3} is specified. - @end table @node ARM Options @@ -10095,6 +10088,13 @@ This is enabled by default on targets (uClinux, SymbianOS) where the runtime loader imposes this restriction, and when @option{-fpic} or @option{-fPIC} is specified. +@item -mfix-cortex-m3-ldrd +@opindex mfix-cortex-m3-ldrd +Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions +with overlapping destination and base registers are used. This option avoids +generating these instructions. This option is enabled by default when +@option{-mcpu=cortex-m3} is specified. + @end table @node AVR Options |