RISC-V: Refine the testcases for cond_widen_complicate-3

Rearrange the test cases of cond_widen_complicate-3 by different types
into different files, instead of put all types together.  Then we can
easily reduce the range when asm check fails.

The below test suites are passed locally, let's wait online CI says.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: Removed.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

10 files changed, 93 insertions, 36 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c
new file mode 100644
index 0000000..e4ff310
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
+
+#include "cond_widen_complicate-3.h"
+
+TEST_TYPE (float, _Float16)
+
+/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c
new file mode 100644
index 0000000..7d2b448
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-f32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
+
+#include "cond_widen_complicate-3.h"
+
+TEST_TYPE (double, float)
+
+/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c
new file mode 100644
index 0000000..dc7e1da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
+
+#include "cond_widen_complicate-3.h"
+
+TEST_TYPE (int32_t, int16_t)
+
+/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c
new file mode 100644
index 0000000..de1072f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
+
+#include "cond_widen_complicate-3.h"
+
+TEST_TYPE (int64_t, int32_t)
+
+/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c
new file mode 100644
index 0000000..8de5ef4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-i8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
+
+#include "cond_widen_complicate-3.h"
+
+TEST_TYPE (int16_t, int8_t)
+
+/* { dg-final { scan-assembler-times {\tvwmul\.vv} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c
new file mode 100644
index 0000000..a4aafd2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
+
+#include "cond_widen_complicate-3.h"
+
+TEST_TYPE (uint32_t, uint16_t)
+
+/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c
new file mode 100644
index 0000000..0deeaa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
+
+#include "cond_widen_complicate-3.h"
+
+TEST_TYPE (uint64_t, uint32_t)
+
+/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c
new file mode 100644
index 0000000..a6afcd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3-u8.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d -mrvv-vector-bits=scalable" } */
+
+#include "cond_widen_complicate-3.h"
+
+TEST_TYPE (uint16_t, uint8_t)
+
+/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
deleted file mode 100644
index d02a8e2..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -ffast-math" } */
-
-#include <stdint-gcc.h>
-
-#define TEST_TYPE(TYPE1, TYPE2)                                                \
-  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
-    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
-    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b,          \
-    TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
-  {                                                                            \
-    for (int i = 0; i < n; i++)                                                \
-      {                                                                        \
-	dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i];               \
-	dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i];            \
-	dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i];            \
-	dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i];            \
-      }                                                                        \
-  }
-
-#define TEST_ALL()                                                             \
-  TEST_TYPE (int16_t, int8_t)                                                  \
-  TEST_TYPE (uint16_t, uint8_t)                                                \
-  TEST_TYPE (int32_t, int16_t)                                                 \
-  TEST_TYPE (uint32_t, uint16_t)                                               \
-  TEST_TYPE (int64_t, int32_t)                                                 \
-  TEST_TYPE (uint64_t, uint32_t)                                               \
-  TEST_TYPE (float, _Float16)                                                  \
-  TEST_TYPE (double, float)
-
-TEST_ALL ()
-
-/* { dg-final { scan-assembler-times {\tvwmul\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 8 } } */
-/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h
new file mode 100644
index 0000000..974846f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.h
@@ -0,0 +1,21 @@
+#ifndef COND_WIDEN_COMPLICATE_3_H
+#define COND_WIDEN_COMPLICATE_3_H
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2)                                                \
+  __attribute__ ((noipa)) void vwadd_##TYPE1##_##TYPE2 (                       \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b,          \
+    TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      {                                                                        \
+	dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i];               \
+	dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i];            \
+	dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i];            \
+	dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i];            \
+      }                                                                        \
+  }
+
+#endif