RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7

This patch will add testcase for unsigned integer SAT_ADD form 7:

  #define DEF_SAT_U_ADD_FMT_7(WT, T)     \
  T __attribute__((noinline))            \
  sat_u_add_##WT##_##T##_fmt_7(T x, T y) \
  {                                      \
    T max = -1;                          \
    WT val = (WT)x + (WT)y;              \
    return val > max ? max : (T)val;     \
  }

  DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t)

The below test are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c: New test.
	* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

13 files changed, 299 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
index c8a135a..2225d30 100644
--- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h
@@ -53,12 +53,34 @@ sat_u_add_##T##_fmt_6 (T x, T y)        \
   return (T)(x + y) < x ? -1 : (x + y); \
 }
 
+#define DEF_SAT_U_ADD_FMT_7(WT, T)     \
+T __attribute__((noinline))            \
+sat_u_add_##WT##_##T##_fmt_7(T x, T y) \
+{                                      \
+  T max = -1;                          \
+  WT val = (WT)x + (WT)y;              \
+  return val > max ? max : (T)val;     \
+}
+#define DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) DEF_SAT_U_ADD_FMT_7(WT, T)
+
 #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y)
 #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y)
 #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y)
 #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y)
 #define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y)
 #define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) \
+  sat_u_add_uint16_t_##T##_fmt_7(x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T, x, y) \
+  RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y) \
+  sat_u_add_uint32_t_##T##_fmt_7(x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T, x, y) \
+  RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) \
+  sat_u_add_uint64_t_##T##_fmt_7(x, y)
+#define RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T, x, y) \
+  RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y)
 
 #define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM)      \
 T __attribute__((noinline))                  \
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c
new file mode 100644
index 0000000..527f8de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint32_t_uint16_t_fmt_7:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_FMT_7(uint32_t, uint16_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c
new file mode 100644
index 0000000..e9031de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint64_t_uint16_t_fmt_7:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_ADD_FMT_7(uint64_t, uint16_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c
new file mode 100644
index 0000000..a71bd2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint64_t_uint32_t_fmt_7:
+** slli\s+[atx][0-9]+,\s*a0,\s*32
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32
+** add\s+[atx][0-9]+,\s*a[01],\s*a[01]
+** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c
new file mode 100644
index 0000000..5892986
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint16_t_uint8_t_fmt_7:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_FMT_7(uint16_t, uint8_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c
new file mode 100644
index 0000000..a42a712
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint32_t_uint8_t_fmt_7:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_FMT_7(uint32_t, uint8_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c
new file mode 100644
index 0000000..f37ef1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_add_uint64_t_uint8_t_fmt_7:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_ADD_FMT_7(uint64_t, uint8_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c
new file mode 100644
index 0000000..25dc1d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint16_t
+#define WT             uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP
+
+DEF_SAT_U_ADD_FMT_7_WRAP(WT, T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      1, },
+  {      1,     1,      2, },
+  {      0, 65534,  65534, },
+  {      1, 65534,  65535, },
+  {      2, 65534,  65535, },
+  {      0, 65535,  65535, },
+  {      1, 65535,  65535, },
+  {      2, 65535,  65535, },
+  {  65535, 65535,  65535, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c
new file mode 100644
index 0000000..565b108
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint16_t
+#define WT             uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP
+
+DEF_SAT_U_ADD_FMT_7_WRAP(WT, T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      1, },
+  {      1,     1,      2, },
+  {      0, 65534,  65534, },
+  {      1, 65534,  65535, },
+  {      2, 65534,  65535, },
+  {      0, 65535,  65535, },
+  {      1, 65535,  65535, },
+  {      2, 65535,  65535, },
+  {  65535, 65535,  65535, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c
new file mode 100644
index 0000000..6ff34fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint32_t
+#define WT             uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP
+
+DEF_SAT_U_ADD_FMT_7_WRAP(WT, T)
+
+T test_data[][3] = {
+  /*     arg_0,      arg_1,      expect */
+  {          0,          0,           0, },
+  {          0,          1,           1, },
+  {          1,          1,           2, },
+  {          0, 4294967294,  4294967294, },
+  {          1, 4294967294,  4294967295, },
+  {          2, 4294967294,  4294967295, },
+  {          0, 4294967295,  4294967295, },
+  {          1, 4294967295,  4294967295, },
+  {          2, 4294967295,  4294967295, },
+  { 4294967295, 4294967295,  4294967295, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c
new file mode 100644
index 0000000..9e6e70a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint8_t
+#define WT             uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP
+
+DEF_SAT_U_ADD_FMT_7_WRAP(WT, T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      1, },
+  {      1,     1,      2, },
+  {      0,   254,    254, },
+  {      1,   254,    255, },
+  {      2,   254,    255, },
+  {      0,   255,    255, },
+  {      1,   255,    255, },
+  {      2,   255,    255, },
+  {    255,   255,    255, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c
new file mode 100644
index 0000000..a1134ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint8_t
+#define WT             uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP
+
+DEF_SAT_U_ADD_FMT_7_WRAP(WT, T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      1, },
+  {      1,     1,      2, },
+  {      0,   254,    254, },
+  {      1,   254,    255, },
+  {      2,   254,    255, },
+  {      0,   255,    255, },
+  {      1,   255,    255, },
+  {      2,   255,    255, },
+  {    255,   255,    255, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c
new file mode 100644
index 0000000..ef9f7aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c
@@ -0,0 +1,26 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint8_t
+#define WT             uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP
+
+DEF_SAT_U_ADD_FMT_7_WRAP(WT, T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      1, },
+  {      1,     1,      2, },
+  {      0,   254,    254, },
+  {      1,   254,    255, },
+  {      2,   254,    255, },
+  {      0,   255,    255, },
+  {      1,   255,    255, },
+  {      2,   255,    255, },
+  {    255,   255,    255, },
+};
+
+#include "scalar_sat_binary.h"