aarch64: Prevent FPR register asms for +nofp

+nofp disabled the automatic allocation of FPRs, but it didn't stop
users from explicitly putting register variables in FPRs.  We'd then
either report an ICE or generate unsupported instructions.

It's still possible (and deliberately redundant) to specify FPRs in
clobber lists.

gcc/
	* config/aarch64/aarch64.cc (aarch64_conditional_register_usage):
	Disallow use of FPRs in register asms for !TARGET_FLOAT.

gcc/testsuite/
	* gcc.target/aarch64/nofp_2.c: New test.

2 files changed, 20 insertions, 0 deletions

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 566763c..786ede7 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -19847,6 +19847,7 @@ aarch64_conditional_register_usage (void)
 	{
 	  fixed_regs[i] = 1;
 	  call_used_regs[i] = 1;
+	  CLEAR_HARD_REG_BIT (operand_reg_set, i);
 	}
     }
   if (!TARGET_SVE)
diff --git a/gcc/testsuite/gcc.target/aarch64/nofp_2.c b/gcc/testsuite/gcc.target/aarch64/nofp_2.c
new file mode 100644
index 0000000..8a262cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/nofp_2.c
@@ -0,0 +1,19 @@
+/* { dg-options "" } */
+
+#pragma GCC target "+nothing+nofp"
+
+void
+test (void)
+{
+  register int q0 asm ("q0"); // { dg-error "not general enough" }
+  register int q1 asm ("q1"); // { dg-error "not general enough" }
+  asm volatile ("" : "=w" (q0));
+  q1 = q0;
+  asm volatile ("" :: "w" (q1));
+}
+
+void
+ok (void)
+{
+  asm volatile ("" ::: "q0");
+}