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authorClaudiu Zissulescu <claziss@synopsys.com>2017-11-30 15:42:22 +0100
committerClaudiu Zissulescu <claziss@gcc.gnu.org>2017-11-30 15:42:22 +0100
commitf521d500fcfe4be65d4d00784633d504a635ae17 (patch)
tree5a002eb964193811231f6574e35a1b0298dfae94 /gcc
parenta09202439b038a7e92900bdbe5aa6488b9409a18 (diff)
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[ARC] Add trap instruction.
2017-11-07 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (trap): New pattern. From-SVN: r255276
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/config/arc/arc.md7
2 files changed, 11 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ae502ca..aee1325 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
2017-11-30 Claudiu Zissulescu <claziss@synopsys.com>
+ * config/arc/arc.md (trap): New pattern.
+
+2017-11-30 Claudiu Zissulescu <claziss@synopsys.com>
+
* config/arc/arc.c (hwloop_optimize): Prevent the last ZOL
instruction to end into a delay slot.
* config/arc/arc.md (cond_delay_insn): Check if the instruction
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index b39f047..880327c 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4301,6 +4301,13 @@
; use it for lack of inter-procedural branch shortening.
; Link-time relaxation would help...
+(define_insn "trap"
+ [(trap_if (const_int 1) (const_int 0))]
+ "!TARGET_ARC600_FAMILY"
+ "trap_s\\t5"
+ [(set_attr "type" "misc")
+ (set_attr "length" "2")])
+
(define_insn "nop"
[(const_int 0)]
""