Daily bump.

7 files changed, 405 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6a26f87..f42adeb 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,195 @@
+2024-12-03  Georg-Johann Lay  <avr@gjlay.de>
+
+	* config/avr/avr.cc (avr_insn_location): New variable.
+	(avr_final_prescan_insn): Set avr_insn_location.
+	(avr_asm_final_postscan_insn): Unset avr_insn_location after last insn.
+	(avr_print_operand): Pass avr_insn_location to warning_at.
+
+2024-12-03  David Malcolm  <dmalcolm@redhat.com>
+
+	* doc/libgdiagnostics/conf.py: Remove "author".  Change
+	"copyright" field to the FSF.
+
+2024-12-03  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/117726
+	* config/avr/avr-passes.cc (avr_split_shift_p)
+	[ASHIFT, LSHIFTRT]: Allow offsets of bitsize - 1.
+	(avr_split_shift4) [ASHIFT, LSHIFTRT]: Also split offset 31.
+	(avr_split_shift3) [ASHIFT, LSHIFTRT]: Also split offset 23.
+	(avr_split_shift2) [ASHIFT, LSHIFTRT]: Also split offset 15.
+
+2024-12-03  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/117874
+	* tree-vect-slp.cc (vect_build_slp_tree_2): Perform early
+	reassoc checks before eating into discovery limit.
+
+2024-12-03  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/117874
+	* tree-vectorizer.h (vec_info_shared::n_stmts): Remove.
+	(LOOP_VINFO_N_STMTS): Likewise.
+	* tree-vectorizer.cc (vec_info_shared::vec_info_shared): Adjust.
+	* tree-vect-loop.cc (vect_get_datarefs_in_loop): Do not
+	count stmts.
+	(vect_analyze_loop_2): Adjust.  Pass stmt_vec_info.length ()
+	to vect_analyze_slp as SLP tree size limit.
+
+2024-12-03  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR target/117726
+	* config/avr/avr-passes.cc (avr_emit_shift): All 8-bit shifts with
+	an offset of 6 have 3-operand alternatives.
+	* config/avr/avr.cc (ashlqi3_out, lshrqi3_out) [case 6]:
+	Implement as 3-operand insn.
+	(avr_rtx_costs_1) [QImode, ASHIFT + LSHIFTRT]: Adjust
+	costs for offset of 6.
+	* config/avr/avr.md (*ashlqi3_split, *ashlqi3)
+	(*lshrqi3_split, *lshrqi3): Add "r,r,C06" alternative.
+
+2024-12-03  Claudio Bantaloukas  <claudio.bantaloukas@arm.com>
+
+	* config/aarch64/aarch64-option-extensions.def: (fp8): fix FEATURE_STRING.
+	(fp8fma, ssve-fp8fma): Likewise.
+	(fp8dot4, ssve-fp8dot4, fp8dot2, ssve-fp8dot2): Likewise.
+
+2024-12-03  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/117420
+	* tree-ssanames.h (get_known_nonzero_bits): Declare.
+	* tree-ssanames.cc (get_nonzero_bits): New wrapper function.  Move old
+	definition to ...
+	(get_nonzero_bits_1): ... here, add static.  Change widest_int in
+	function comment to wide_int.
+	(get_known_nonzero_bits_1, get_known_nonzero_bits): New functions.
+	* match.pd (with_possible_nonzero_bits2): Rename to ...
+	(with_possible_nonzero_bits): ... this.  Guard the bit_and case with
+	#if GENERIC.  Change to a normal match predicate without parameters.
+	Rename the old with_possible_nonzero_bits match to ...
+	(with_possible_nonzero_bits_1): ... this.
+	(with_certain_nonzero_bits2): Remove.
+	(with_known_nonzero_bits_1, with_known_nonzero_bits): New match
+	predicates.
+	(X == C (or X & Z == Y | C) is impossible if ~nonzero(X) & C != 0):
+	Use with_known_nonzero_bits@0 instead of
+	(with_certain_nonzero_bits2 @1), use with_possible_nonzero_bits@0
+	instead of (with_possible_nonzero_bits2 @0) and
+	get_known_nonzero_bits (@1) instead of wi::to_wide (@1).
+
+2024-12-03  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/117847
+	* gimple-lower-bitint.cc (gimple_lower_bitint) <case LROTATE_EXPR>:
+	Use m = (p - n) % p instead of m = p - n for the other shift count.
+
+2024-12-03  Tobias Burnus  <tburnus@baylibre.com>
+
+	* cgraphunit.cc (varpool_node::finalize_decl): Set alignment
+	based on OpenMP's 'omp allocate' attribute/directive.
+
+2024-12-03  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-simd-pragma-builtins.def: Add a flags
+	field to each entry.
+	* config/aarch64/aarch64-builtins.cc: Update includes accordingly.
+	(aarch64_pragma_builtins_data): Add a flags field.
+	(aarch64_init_pragma_builtins): Use the flags field to add attributes
+	to the function declaration.
+
+2024-12-03  Saurabh Jha  <saurabh.jha@arm.com>
+	    Vladimir Miloserdov  <vladimir.miloserdov@arm.com>
+	    Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-builtins.cc
+	(aarch64_builtin_signatures): Add binary_lane.
+	(aarch64_fntype): Handle it.
+	(simd_types): Add 16-bit x2 types.
+	(aarch64_pragma_builtins_checker): New class.
+	(aarch64_general_check_builtin_call): Use it.
+	(aarch64_expand_pragma_builtin): Add support for lut unspecs.
+	* config/aarch64/aarch64-option-extensions.def
+	(AARCH64_OPT_EXTENSION): Add lut option.
+	* config/aarch64/aarch64-simd-pragma-builtins.def
+	(ENTRY_BINARY_LANE): Modify to use new ENTRY macro.
+	(ENTRY_TERNARY_VLUT8): Macro to declare lut intrinsics.
+	(ENTRY_TERNARY_VLUT16): Macro to declare lut intrinsics.
+	(REQUIRED_EXTENSIONS): Declare lut intrinsics.
+	* config/aarch64/aarch64-simd.md
+	(@aarch64_<vluti_uns_op><VLUT:mode><VB:mode>): Instruction
+	pattern for luti2 and luti4 intrinsics.
+	(@aarch64_lutx2<VLUT:mode><VB:mode>): Instruction pattern for
+	luti4x2 intrinsics.
+	* config/aarch64/aarch64.h
+	(TARGET_LUT): lut flag.
+	* config/aarch64/iterators.md: Iterators and attributes for lut.
+	* doc/invoke.texi: Document extension in AArch64 Options.
+
+2024-12-03  Saurabh Jha  <saurabh.jha@arm.com>
+	    Vladimir Miloserdov  <vladimir.miloserdov@arm.com>
+	    Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-builtins.cc
+	(ENTRY): Modify to add support of return and argument types.
+	(struct simd_type): New struct to declare types using mode and
+	qualifiers.
+	(struct aarch64_pragma_builtins_data): Replace mode with
+	the array of types to support return and argument types.
+	(aarch64_fntype): Modify to handle different signatures.
+	(aarch64_expand_pragma_builtin): Modify to handle different
+	signatures.
+	* config/aarch64/aarch64-simd-pragma-builtins.def
+	(ENTRY_VHSDF): Rename to ENTRY_BINARY_VHSDF.
+	(ENTRY_BINARY): New macro to declare binary intrinsics.
+	(ENTRY_BINARY_VHSDF): Remove signature argument and use
+	ENTRY_BINARY.
+
+2024-12-03  Saurabh Jha  <saurabh.jha@arm.com>
+	    Vladimir Miloserdov  <vladimir.miloserdov@arm.com>
+	    Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/iterators.md: Reorder some declarations,
+	putting them under the associated heading comment.
+
+2024-12-03  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-protos.h (aarch64_v64_mode): Declare.
+	(aarch64_vq_mode): Rename to...
+	(aarch64_v128_mode): ...this.
+	* config/aarch64/aarch64.cc (aarch64_v64_mode): New function,
+	split out from...
+	(aarch64_simd_container_mode): ...here.
+	(aarch64_vq_mode): Rename to...
+	(aarch64_v128_mode): ...this and update callers.
+	* config/aarch64/aarch64-sve-builtins-base.cc: Likewise update calls.
+
+2024-12-03  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64-sve-builtins.cc (report_non_ice)
+	(report_out_of_range, report_neither_nor, report_not_one_of)
+	(report_not_enum): Move to...
+	* config/aarch64/aarch64.cc: ...here, putting them in the aarch64
+	namespace, and...
+	* config/aarch64/aarch64-protos.h: ...declare them here.
+
+2024-12-03  Pan Li  <pan2.li@intel.com>
+
+	* match.pd: Refactor sorts of unsigned SAT_SUB match patterns.
+
+2024-12-03  Heiko Eißfeldt  <heiko@hexco.de>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/114540
+	* varasm.cc (decode_reg_name_and_count): Use strtoul instead of atoi
+	and simplify verification that the whole asmspec contains just decimal
+	digits.
+
+2024-12-03  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/117874
+	* tree-vect-loop.cc (vect_analyze_loop_2): When non-SLP
+	analysis fails, try single-lane SLP.
+
 2024-12-02  David Malcolm  <dmalcolm@redhat.com>
 
 	* doc/libgdiagnostics/tutorial/01-hello-world.rst: Update linker
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index ba18418..74f6fd4 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20241203
+20241204
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 6ecadeb..037b4ac 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,8 @@
+2024-12-03  Tobias Burnus  <tburnus@baylibre.com>
+
+	* c-parser.cc (c_parser_omp_allocate): Only check scope if
+	not in_omp_decl_attribute. Remove setting the alignment.
+
 2024-11-30  Martin Uecker  <uecker@tugraz.at>
 
 	PR c/117806
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 59fbce8..0bcd7d1 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,10 @@
+2024-12-03  Nina Ranns  <dinka.ranns@googlemail.com>
+
+	PR c++/117579
+	* parser.cc (cp_parser_statement): Replace assertion with a
+	conditional check that the statement containing a contract assert
+	is empty.
+
 2024-12-02  Patrick Palka  <ppalka@redhat.com>
 
 	* constraint.cc (resolve_concept_check): Remove.
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 2f4e492..86b70c7 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,40 @@
+2024-12-03  Paul Thomas  <pault@gcc.gnu.org>
+
+	PR fortran/102689
+	* trans-array.cc (get_array_ref_dim_for_loop_dim): Use the arg1
+	class container carried in ss->info as the seed for a lhs in
+	class valued transformational intrinsic calls that are not the
+	rhs of an assignment. Otherwise, the lhs variable expression is
+	taken from the loop chain. For this latter case, the _vptr and
+	_len fields are set.
+	(gfc_trans_create_temp_array): Use either the lhs expression
+	seeds to build a class variable that will take the returned
+	descriptor as its _data field. In the case that the arg1 expr.
+	is used, 'atmp' must be marked as unused, a typespec built with
+	the correct rank and the _vptr and _len fields set. The element
+	size is provided for the temporary allocation and to set the
+	descriptor span.
+	(gfc_array_init_size): When an intrinsic type scalar expr3 is
+	used in allocation of a class array, use its element size in
+	the descriptor dtype.
+	* trans-expr.cc (gfc_conv_class_to_class): Class valued
+	transformational intrinsics return the pointer to the array
+	descriptor as the _data field of a class temporary. Extract
+	directly and return the address of the class temporary.
+	(gfc_conv_procedure_call): store the expression for the first
+	argument of a class valued transformational intrinsic function
+	in the ss info class_container field. Later, use its type  as
+	the element type in the call to gfc_trans_create_temp_array.
+	(fcncall_realloc_result): Add a dtype argument and use it in
+	the descriptor, when available.
+	(gfc_trans_arrayfunc_assign): For class lhs, build a dtype with
+	the lhs rank and the rhs element size and use it in the call to
+	fcncall_realloc_result.
+
+2024-12-03  Tobias Burnus  <tburnus@baylibre.com>
+
+	* trans-decl.cc (gfc_finish_var_decl): Remove setting the alignment.
+
 2024-11-29  Andrew Pinski  <quic_apinski@quicinc.com>
 
 	PR fortran/117843
diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog
index 5bd1cb1..70a7e23 100644
--- a/gcc/po/ChangeLog
+++ b/gcc/po/ChangeLog
@@ -1,3 +1,7 @@
+2024-12-03  Joseph Myers  <josmyers@redhat.com>
+
+	* zh_CN.po: Update.
+
 2024-09-19  Joseph Myers  <josmyers@redhat.com>
 
 	* zh_CN.po: Update.
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 22f492e..3b267f8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,162 @@
+2024-12-03  Georg-Johann Lay  <avr@gjlay.de>
+
+	PR testsuite/52641
+	PR testsuite/109123
+	PR testsuite/114661
+	PR testsuite/117828
+	PR testsuite/116481
+	PR testsuite/91069
+	* gcc.dg/Wuse-after-free-pr109123.c: Use size_t
+	instead of long unsigned int.
+	* gcc.dg/c23-tag-bitfields-1.c: Requires int32plus.
+	* gcc.dg/pr114661.c: Same.
+	* gcc.dg/pr117828.c: Same.
+	* gcc.dg/flex-array-counted-by-2.c: Use uintptr_t
+	instead of unsigned long.
+	* gcc.dg/pr116481.c: Same.
+	* gcc.dg/lto/tag-1_0.c: Use int32_t instead of int.
+	* gcc.dg/lto/tag-1_1.c: Use int16_t instead of short.
+	* gcc.dg/pr91069.c: Require double64.
+	* gcc.dg/type-convert-var.c: Require double64plus.
+
+2024-12-03  Georg-Johann Lay  <avr@gjlay.de>
+
+	* gcc.c-torture/execute/ieee/cdivchkd.x: New file.
+	* gcc.c-torture/execute/ieee/cdivchkf.x: New file.
+	* gcc.dg/flex-array-counted-by.c: Require wchar.
+	* gcc.dg/fold-copysign-1.c [avr]: Add -mdouble=64.
+
+2024-12-03  Georg-Johann Lay  <avr@gjlay.de>
+
+	* gcc.dg/Warray-bounds-33.c: Adjust for avr diagnostics.
+	* gcc.dg/pr56228.c: Same.
+	* gcc.dg/pr86124.c: Same.
+	* gcc.dg/pr94291.c: Same.
+	* gcc.dg/tree-ssa/pr82059.c: Same.
+
+2024-12-03  Jeff Law  <jlaw@ventanamicro.com>
+
+	* gcc.dg/crc-linux-1.c: Moved to from gcc.dg/torture.
+	* gcc.dg/crc-linux-2.c: Likewise.
+	* gcc.dg/crc-linux-4.c: Likewise.
+	* gcc.dg/crc-linux-5.c: Likewise.
+	* gcc.dg/crc-not-crc-15.c: Likewise.
+	* gcc.dg/crc-side-instr-1.c: Likewise.
+	* gcc.dg/crc-side-instr-2.c: Likewise.
+	* gcc.dg/crc-side-instr-3.c: Likewise.
+	* gcc.dg/crc-side-instr-4.c: Likewise.
+	* gcc.dg/crc-side-instr-5.c: Likewise.
+	* gcc.dg/crc-side-instr-6.c: Likewise.
+	* gcc.dg/crc-side-instr-7.c: Likewise.
+	* gcc.dg/crc-side-instr-8.c: Likewise.
+	* gcc.dg/crc-side-instr-9.c: Likewise.
+	* gcc.dg/crc-side-instr-10.c: Likewise.
+	* gcc.dg/crc-side-instr-11.c: Likewise.
+	* gcc.dg/crc-side-instr-12.c: Likewise.
+	* gcc.dg/crc-side-instr-13.c: Likewise.
+	* gcc.dg/crc-side-instr-14.c: Likewise.
+	* gcc.dg/crc-side-instr-15.c: Likewise.
+	* gcc.dg/crc-side-instr-16.c: Likewise.
+	* gcc.dg/crc-side-instr-17.c: Likewise.
+	* gcc.dg/torture/crc-linux-1.c: New file.
+	* gcc.dg/torture/crc-linux-2.c: New file.
+	* gcc.dg/torture/crc-linux-4.c: New file.
+	* gcc.dg/torture/crc-linux-5.c: New file.
+	* gcc.dg/torture/crc-not-crc-15.c: New file.
+	* gcc.dg/torture/crc-side-instr-1.c: New file.
+	* gcc.dg/torture/crc-side-instr-10.c: New file.
+	* gcc.dg/torture/crc-side-instr-11.c: New file.
+	* gcc.dg/torture/crc-side-instr-12.c: New file.
+	* gcc.dg/torture/crc-side-instr-13.c: New file.
+	* gcc.dg/torture/crc-side-instr-14.c: New file.
+	* gcc.dg/torture/crc-side-instr-15.c: New file.
+	* gcc.dg/torture/crc-side-instr-16.c: New file.
+	* gcc.dg/torture/crc-side-instr-17.c: New file.
+	* gcc.dg/torture/crc-side-instr-2.c: New file.
+	* gcc.dg/torture/crc-side-instr-3.c: New file.
+	* gcc.dg/torture/crc-side-instr-4.c: New file.
+	* gcc.dg/torture/crc-side-instr-5.c: New file.
+	* gcc.dg/torture/crc-side-instr-6.c: New file.
+	* gcc.dg/torture/crc-side-instr-7.c: New file.
+	* gcc.dg/torture/crc-side-instr-8.c: New file.
+	* gcc.dg/torture/crc-side-instr-9.c: New file.
+
+2024-12-03  Nina Ranns  <dinka.ranns@googlemail.com>
+
+	PR c++/117579
+	* g++.dg/contracts/pr117579.C: New test.
+
+2024-12-03  Edwin Lu  <ewlu@rivosinc.com>
+
+	* gcc.target/riscv/crc-builtin-zbc32.c: Fix selector.
+	* gcc.target/riscv/crc-builtin-zbc64.c: Ditto.
+
+2024-12-03  Paul Thomas  <pault@gcc.gnu.org>
+
+	PR fortran/102689
+	* gfortran.dg/class_transformational_1.f90: New test for class-
+	valued reshape.
+	* gfortran.dg/class_transformational_2.f90: New test for other
+	class_valued transformational intrinsics.
+
+2024-12-03  Joseph Myers  <josmyers@redhat.com>
+
+	PR c/117162
+	* gcc.dg/cpp/c17-ucn-1.c, gcc.dg/cpp/c17-ucn-2.c,
+	gcc.dg/cpp/c17-ucn-3.c, gcc.dg/cpp/c17-ucn-4.c,
+	gcc.dg/cpp/c23-ucn-2.c, gcc.dg/cpp/c23-ucnid-2.c: New tests.
+	* c-c++-common/cpp/delimited-escape-seq-3.c,
+	c-c++-common/cpp/named-universal-char-escape-3.c,
+	gcc.dg/cpp/c23-ucn-1.c, gcc.dg/cpp/c2y-delimited-escape-seq-3.c:
+	Update expected messages
+	* gcc.dg/cpp/ucs.c: Use -pedantic-errors.  Update expected
+	messages.
+
+2024-12-03  Jakub Jelinek  <jakub@redhat.com>
+
+	PR tree-optimization/117420
+	* gcc.dg/tree-ssa/pr117420.c: New test.
+
+2024-12-03  Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/117847
+	* gcc.dg/torture/bitint-75.c: New test.
+
+2024-12-03  Tobias Burnus  <tburnus@baylibre.com>
+
+	* c-c++-common/gomp/allocate-18.c: Check that alignof is unaffected
+	by 'omp allocate'.
+	* c-c++-common/gomp/allocate-19.c: Likewise.
+
+2024-12-03  Saurabh Jha  <saurabh.jha@arm.com>
+	    Vladimir Miloserdov  <vladimir.miloserdov@arm.com>
+	    Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/simd/lut-incorrect-range.c: New test.
+	* gcc.target/aarch64/simd/lut-no-flag.c: New test.
+	* gcc.target/aarch64/simd/lut.c: New test.
+
+2024-12-03  Pan Li  <pan2.li@intel.com>
+
+	* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
+	options passing to testcases.
+
+2024-12-03  Heiko Eißfeldt  <heiko@hexco.de>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	PR middle-end/114540
+	* gcc.dg/pr114540.c: New test.
+
+2024-12-03  Richard Biener  <rguenther@suse.de>
+
+	PR tree-optimization/117874
+	* gcc.dg/vect/pr117874.c: New testcase.
+
+2024-12-03  Pan Li  <pan2.li@intel.com>
+
+	* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
+	options passing to testcases.
+
 2024-12-02  Jakub Jelinek  <jakub@redhat.com>
 
 	* g++.target/aarch64/pr94515-2.C: Add newline at the end of the file.