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| author | Richard Sandiford <richard.sandiford@linaro.org> | 2017-11-07 16:08:47 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2017-11-07 16:08:47 +0000 |
| commit | f32c3adb8d77c0ebee112ecf26ae249c8574970e (patch) | |
| tree | 5f2c9635d4a53a4d6b1b5fb91ec16b1e94e1d25d /gcc | |
| parent | 56ccfbd6085be730876ebab31f865e4499b27067 (diff) | |
| download | gcc-f32c3adb8d77c0ebee112ecf26ae249c8574970e.zip gcc-f32c3adb8d77c0ebee112ecf26ae249c8574970e.tar.gz gcc-f32c3adb8d77c0ebee112ecf26ae249c8574970e.tar.bz2 | |
[AArch64] Use aarch64_reg_or_imm instead of nonmemory_operand
Some of the shift expanders accepted nonmemory_operands but were only
able to handle register_operands or CONST_INTs. This is probably
academic without SVE, since we're not likely to see shifts by other
types of constant (const_wide_ints, consts, etc). But for SVE,
it's possible for a vectorised shift induction to have a CONST_POLY_INT
shift amount.
This patch makes the expanders use aarch64_reg_or_imm instead.
2017-11-07 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3)
(rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of
nonmmory_operand.
From-SVN: r254499
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 6 |
2 files changed, 9 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f81b5d8..db9ff08 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-11-07 Richard Sandiford <richard.sandiford@linaro.org> + + * config/aarch64/aarch64.md (ashl<mode>3, ashr<mode>3, lshr<mode>3) + (rotr<mode>3, rotl<mode>3): Use aarch64_reg_or_imm instead of + nonmmory_operand. + 2017-11-07 Richard Biener <rguenther@suse.de> * match.pd: Fix build. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index ce75cf4..423a335 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3958,7 +3958,7 @@ (define_expand "<optab><mode>3" [(set (match_operand:GPI 0 "register_operand") (ASHIFT:GPI (match_operand:GPI 1 "register_operand") - (match_operand:QI 2 "nonmemory_operand")))] + (match_operand:QI 2 "aarch64_reg_or_imm")))] "" { if (CONST_INT_P (operands[2])) @@ -3994,7 +3994,7 @@ (define_expand "rotr<mode>3" [(set (match_operand:GPI 0 "register_operand") (rotatert:GPI (match_operand:GPI 1 "register_operand") - (match_operand:QI 2 "nonmemory_operand")))] + (match_operand:QI 2 "aarch64_reg_or_imm")))] "" { if (CONST_INT_P (operands[2])) @@ -4014,7 +4014,7 @@ (define_expand "rotl<mode>3" [(set (match_operand:GPI 0 "register_operand") (rotatert:GPI (match_operand:GPI 1 "register_operand") - (match_operand:QI 2 "nonmemory_operand")))] + (match_operand:QI 2 "aarch64_reg_or_imm")))] "" { /* (SZ - cnt) % SZ == -cnt % SZ */ |