[PATCH][v5] RISC-V: add option -m(no-)autovec-segment

Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This is useful for
performance experiments.

gcc/ChangeLog:
	* config/riscv/autovec.md (vec_mask_len_load_lanes, vec_mask_len_store_lanes):
	Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT
	* config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New macro.
	* config/riscv/riscv.opt (-m(no-)autovec-segment): New option.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c:
	New test.
	* gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c:
	New test.
	* gcc.target/riscv/rvv/autovec/no-segment.c: New test.

68 files changed, 397 insertions, 2 deletions

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 7dc78a4..a34f63c 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -282,7 +282,7 @@
    (match_operand:<VM> 2 "vector_mask_operand")
    (match_operand 3 "autovec_length_operand")
    (match_operand 4 "const_0_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR_AUTOVEC_SEGMENT"
   {
     riscv_vector::expand_lanes_load_store (operands, true);
     DONE;
@@ -295,7 +295,7 @@
    (match_operand:<VM> 2 "vector_mask_operand")
    (match_operand 3 "autovec_length_operand")
    (match_operand 4 "const_0_operand")]
-  "TARGET_VECTOR"
+  "TARGET_VECTOR_AUTOVEC_SEGMENT"
   {
     riscv_vector::expand_lanes_load_store (operands, false);
     DONE;
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 5497d11..1b2a4bc 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -157,4 +157,9 @@ enum riscv_tls_type {
   TLS_DESCRIPTORS
 };
 
+/* On some microarchitectures, vector segment loads and stores are excessively
+   expensive, so predicate the generation of those instrunctions.  */
+#define TARGET_VECTOR_AUTOVEC_SEGMENT					       \
+  (TARGET_VECTOR && riscv_mautovec_segment)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index a8758ab..6360ed39 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -658,3 +658,7 @@ Specify TLS dialect.
 mfence-tso
 Target Var(TARGET_FENCE_TSO) Init(1)
 Specifies whether the fence.tso instruction should be used.
+
+mautovec-segment
+Target Integer Var(riscv_mautovec_segment) Init(1)
+Enable (default) or disable generation of vector segment load/store instructions.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
new file mode 100644
index 0000000..79d0361
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c
@@ -0,0 +1,61 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=scalable -O3 -mno-autovec-segment" } */
+
+enum e { c, d };
+enum g { f };
+
+struct h
+{
+  float x, w;
+};
+
+struct k
+{
+  short z, y, i, j;
+};
+
+long r;
+struct h m, p;
+struct k *q;
+
+short
+l (float s)
+{
+  if (s <= 0.0f)
+    return 0;
+
+  if (s >= 5)
+    return 5;
+
+  return s;
+}
+
+struct n
+{
+  enum g colorspace;
+};
+
+struct n o (struct k *s, struct h *t)
+{
+  t->w = s->z;
+}
+
+void
+ClutImageChannel (struct n *s, enum e t)
+{
+
+  while (s)
+    for (; r; r++)
+      {
+	o (q, &p);
+
+	if (t & d)
+	  q->y = (&m + q->y)->x;
+
+	if (t)
+	  q->z = l ((&m + q->z)->w);
+
+	if (s->colorspace)
+	  q++;
+      }
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
new file mode 100644
index 0000000..48b8a8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
new file mode 100644
index 0000000..acd2625
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
new file mode 100644
index 0000000..43ba9d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
new file mode 100644
index 0000000..b32257e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
new file mode 100644
index 0000000..41402fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
new file mode 100644
index 0000000..64eb789
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
new file mode 100644
index 0000000..9b20bcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
new file mode 100644
index 0000000..dc577af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
new file mode 100644
index 0000000..0bb4e59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
new file mode 100644
index 0000000..3d70c0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
new file mode 100644
index 0000000..ca98fd5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
new file mode 100644
index 0000000..190b95a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
new file mode 100644
index 0000000..769d709
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
new file mode 100644
index 0000000..bcd31f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_load_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
new file mode 100644
index 0000000..ef40495
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-1.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
new file mode 100644
index 0000000..efb7c21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-2.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
new file mode 100644
index 0000000..ff0f5b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
new file mode 100644
index 0000000..271a239
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-4.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
new file mode 100644
index 0000000..faa5c29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-5.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
new file mode 100644
index 0000000..4188373
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
new file mode 100644
index 0000000..b33541b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
new file mode 100644
index 0000000..ec7b381
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
new file mode 100644
index 0000000..ca3b3d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
new file mode 100644
index 0000000..e4fdea0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
new file mode 100644
index 0000000..7f63d20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
new file mode 100644
index 0000000..df0448d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
new file mode 100644
index 0000000..e6268b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
new file mode 100644
index 0000000..0fdcb8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_store_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "mask_struct_store_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
new file mode 100644
index 0000000..e15eef4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-1.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
new file mode 100644
index 0000000..16aac80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-10.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-10.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
new file mode 100644
index 0000000..2fe0c60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-11.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-11.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
new file mode 100644
index 0000000..b06031e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-12.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-12.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
new file mode 100644
index 0000000..438a123
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-13.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-13.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
new file mode 100644
index 0000000..84afb99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-14.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-14.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
new file mode 100644
index 0000000..62c152b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-15.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-15.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
new file mode 100644
index 0000000..c9c986e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-16.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-16.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
new file mode 100644
index 0000000..b5508b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-17.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-17.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
new file mode 100644
index 0000000..a82a0ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-18.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-18.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
new file mode 100644
index 0000000..001f110
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-2.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
new file mode 100644
index 0000000..08d31f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-3.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-3.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
new file mode 100644
index 0000000..8874b4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-4.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-4.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
new file mode 100644
index 0000000..2e3342d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-5.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect-5.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
+/* { dg-final { scan-assembler-not {vsetvli} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
new file mode 100644
index 0000000..e78d636
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-6.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-6.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
new file mode 100644
index 0000000..9117eea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-7.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-7.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
new file mode 100644
index 0000000..64b5a55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-8.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-8.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
new file mode 100644
index 0000000..94e7ff3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg-9.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-std=c99 -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect-9.c"
+
+/* { dg-final { scan-assembler-not {v[ls]seg[2-8]e[123468]+\.v} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
new file mode 100644
index 0000000..2a50b71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-1.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
new file mode 100644
index 0000000..887a7f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-10.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v && riscv_zvfh } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-10.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
new file mode 100644
index 0000000..f99db9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-11.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-11.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
new file mode 100644
index 0000000..3c32099
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-12.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-12.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
new file mode 100644
index 0000000..588c728
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-13.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-13.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
new file mode 100644
index 0000000..7d4d1bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-14.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-14.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
new file mode 100644
index 0000000..c462a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-15.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-15.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
new file mode 100644
index 0000000..35d0feb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-16.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-16.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
new file mode 100644
index 0000000..4cedba4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-17.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-17.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
new file mode 100644
index 0000000..2bf1cd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-18.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-18.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
new file mode 100644
index 0000000..36772aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-2.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-2.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
new file mode 100644
index 0000000..5820122
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-3.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-3.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
new file mode 100644
index 0000000..4ac2c39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-4.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-4.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
new file mode 100644
index 0000000..dd90a17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-5.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl -funroll-all-loops -fno-schedule-insns -fno-schedule-insns2 -mno-autovec-segment" } */
+
+#include "struct_vect_run-5.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
new file mode 100644
index 0000000..0efbee0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-6.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-6.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
new file mode 100644
index 0000000..c08d1306
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-7.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-7.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
new file mode 100644
index 0000000..404f5d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-8.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-8.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
new file mode 100644
index 0000000..e14ceb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/struct_vect_noseg_run-9.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=scalable -fno-vect-cost-model -mno-autovec-segment" } */
+
+#include "struct_vect_run-9.c"