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| author | Venkataramanan Kumar <venkataramanan.kumar@amd.com> | 2015-06-05 06:38:32 +0000 |
|---|---|---|
| committer | Venkataramanan Kumar <vekumar@gcc.gnu.org> | 2015-06-05 06:38:32 +0000 |
| commit | edf1fd6defa3ed02f1079376b0eecd51cbcb3e44 (patch) | |
| tree | 6613818f014f228c282637b0c4bf5889fdf609be /gcc | |
| parent | 14ae1d88b337dcd79f6bfe29263b8a8ae07c38b3 (diff) | |
| download | gcc-edf1fd6defa3ed02f1079376b0eecd51cbcb3e44.zip gcc-edf1fd6defa3ed02f1079376b0eecd51cbcb3e44.tar.gz gcc-edf1fd6defa3ed02f1079376b0eecd51cbcb3e44.tar.bz2 | |
sse.md (sse3_mwait): Swap the operand constriants.
2015-06-05 Venkataramanan Kumar <venkataramanan.kumar@amd.com>
* config/i386/sse.md (sse3_mwait): Swap the operand constriants.
From-SVN: r224146
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 8 |
2 files changed, 9 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a052bd3..5eb2f40 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2015-06-05 Venkataramanan Kumar <venkataramanan.kumar@amd.com> + + * config/i386/sse.md (sse3_mwait): Swap the operand constriants. + 2015-06-04 DJ Delorie <dj@redhat.com> * config/msp430/msp430.md (movsi_s): New. Special case for diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e44ba9a..4ef51d6 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -13218,10 +13218,12 @@ (set_attr "atom_sse_attr" "fence") (set_attr "memory" "unknown")]) - +;; As per AMD and Intel ISA manuals, the first operand is extensions +;; and it goes to %ecx. The second operand received is hints and it goes +;; to %eax. (define_insn "sse3_mwait" - [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") - (match_operand:SI 1 "register_operand" "c")] + [(unspec_volatile [(match_operand:SI 0 "register_operand" "c") + (match_operand:SI 1 "register_operand" "a")] UNSPECV_MWAIT)] "TARGET_SSE3" ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used. |