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authorJonathan Larmour <jlarmour@cygnus.co.uk>1999-10-21 12:05:58 +0000
committerNick Clifton <nickc@gcc.gnu.org>1999-10-21 12:05:58 +0000
commitec8aac6f55cd0f5e73e57d58f373fc3a0385bcac (patch)
tree1015a0d7d7dca5b334c8b87cad65860a825ca995 /gcc
parent8141abe88d835e30f0a398551244fe0bb63af321 (diff)
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Apply patches submitted by eCos team.
From-SVN: r30120
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog13
-rw-r--r--gcc/config/arm/lib1funcs.asm2
-rw-r--r--gcc/config/arm/telf.h8
-rw-r--r--gcc/config/arm/unknown-elf.h22
4 files changed, 32 insertions, 13 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b67d09c..c8428ad 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+Thu Oct 21 13:03:49 1999 Jonathan Larmour <jlarmour@cygnus.co.uk>
+
+ * config/arm/telf.h (ASM_OUTPUT_SECTION_NAME): Add %nobits option
+ to .section when outputting a .bss section to deal with multiple
+ .bss input sections (as happens with -fdata-sections)
+ Also output %progbits, not @progbits so the assembler doesn't treat as
+ a comment.
+ * config/arm/unknown-elf.h (ASM_OUTPUT_SECTION_NAME): Likewise
+
+ * config/arm/lib1funcs.asm (_call_via_rX): Allow compilation of
+ thumb parts even when building with non-thumb CPUs, by forcing
+ thumb mode.
+
Wed Oct 20 22:57:58 1999 Jeffrey A Law (law@cygnus.com)
* sparc.md (movsf_const_intreg): If splitting, length must be > 1.
diff --git a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm
index 831914b..07b50a7 100644
--- a/gcc/config/arm/lib1funcs.asm
+++ b/gcc/config/arm/lib1funcs.asm
@@ -469,7 +469,7 @@ SYM (__div0):
.text
.align 0
- .code 16
+ .force_thumb
.macro call_via register
.globl SYM (_call_via_\register)
TYPE (_call_via_\register)
diff --git a/gcc/config/arm/telf.h b/gcc/config/arm/telf.h
index 1f7bbb7..ececd53 100644
--- a/gcc/config/arm/telf.h
+++ b/gcc/config/arm/telf.h
@@ -82,11 +82,13 @@ extern int arm_structure_size_boundary;
do \
{ \
if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \
- fprintf (STREAM, "\t.section %s,\"ax\",@progbits\n", (NAME)); \
+ fprintf (STREAM, "\t.section %s,\"ax\",%%progbits\n", NAME); \
else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \
- fprintf (STREAM, "\t.section %s,\"a\"\n", (NAME)); \
+ fprintf (STREAM, "\t.section %s,\"a\"\n", NAME); \
+ else if (! strncmp (NAME, ".bss", 4)) \
+ fprintf (STREAM, "\t.section %s,\"aw\",%%nobits\n", NAME); \
else \
- fprintf (STREAM, "\t.section %s,\"aw\"\n", (NAME)); \
+ fprintf (STREAM, "\t.section %s,\"aw\"\n", NAME); \
} \
while (0)
diff --git a/gcc/config/arm/unknown-elf.h b/gcc/config/arm/unknown-elf.h
index 9e33890..aeddcdf 100644
--- a/gcc/config/arm/unknown-elf.h
+++ b/gcc/config/arm/unknown-elf.h
@@ -89,15 +89,19 @@ func_ptr __DTOR_END__[1] = { (func_ptr) 0 };
NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
NULL_TREE. Some target formats do not support arbitrary sections. Do not
define this macro in such cases. */
-#define ASM_OUTPUT_SECTION_NAME(STREAM, DECL, NAME, RELOC) \
-do { \
- if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \
- fprintf (STREAM, "\t.section %s,\"ax\",@progbits\n", (NAME)); \
- else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \
- fprintf (STREAM, "\t.section %s,\"a\"\n", (NAME)); \
- else \
- fprintf (STREAM, "\t.section %s,\"aw\"\n", (NAME)); \
-} while (0)
+#define ASM_OUTPUT_SECTION_NAME(STREAM, DECL, NAME, RELOC) \
+ do \
+ { \
+ if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL) \
+ fprintf (STREAM, "\t.section %s,\"ax\",%%progbits\n", NAME); \
+ else if ((DECL) && DECL_READONLY_SECTION (DECL, RELOC)) \
+ fprintf (STREAM, "\t.section %s,\"a\"\n", NAME); \
+ else if (! strncmp (NAME, ".bss", 4)) \
+ fprintf (STREAM, "\t.section %s,\"aw\",%%nobits\n", NAME); \
+ else \
+ fprintf (STREAM, "\t.section %s,\"aw\"\n", NAME); \
+ } \
+ while (0)
/* Don't know how to order these. UNALIGNED_WORD_ASM_OP is in
dwarf2.out. */