RISC-V: Fix compress shuffle pattern [PR117383].

This patch makes vcompress use the tail-undisturbed policy by default
and also uses the proper VL.

	PR target/117383

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (enum insn_type): Use TU policy.
	* config/riscv/riscv-v.cc (shuffle_compress_patterns): Set VL.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c:
	Expect tu.
	* gcc.target/riscv/rvv/autovec/pr117383.c: New test.

4 files changed, 53 insertions, 4 deletions

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 98af41c..e36309b 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -509,9 +509,9 @@ enum insn_type : unsigned int
 
   /* For vcompress.vm */
   COMPRESS_OP = __NORMAL_OP_TA2 | BINARY_OP_P,
-  /* has merge operand but use ta.  */
+  /* has merge operand but use tu.  */
   COMPRESS_OP_MERGE
-  = HAS_DEST_P | HAS_MERGE_P | TDEFAULT_POLICY_P | BINARY_OP_P,
+  = HAS_DEST_P | HAS_MERGE_P | TU_POLICY_P | BINARY_OP_P,
 
   /* For vslideup.up has merge operand but use ta.  */
   SLIDEUP_OP_MERGE = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 5fcdaca..417c36a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3393,7 +3393,8 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d)
 
   insn_code icode = code_for_pred_compress (vmode);
   rtx ops[] = {d->target, merge, d->op0, mask};
-  emit_vlmax_insn (icode, COMPRESS_OP_MERGE, ops);
+  emit_nonvlmax_insn (icode, COMPRESS_OP_MERGE, ops,
+		      gen_int_mode (vlen, Pmode));
   return true;
 }
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
index 3654b03..98e53b3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c
@@ -11,7 +11,7 @@ struct s sss[MAX];
 /*
 ** build_linked_list:
 **   ...
-**   vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*ta,\s*ma
+**   vsetivli\s+zero,\s*8,\s*e64,\s*m1,\s*tu,\s*ma
 **   ...
 **   vcompress\.vm\s+v[0-9]+,\s*v[0-9]+,\s*v0
 **   ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117383.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117383.c
new file mode 100644
index 0000000..c01612f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr117383.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-require-effective-target "riscv_v_ok" } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-additional-options "-std=c99 -mrvv-vector-bits=zvl" } */
+
+typedef signed char int8_t;
+typedef int8_t vnx64i __attribute__ ((vector_size (64)));
+
+#define MASK_64                                                                \
+  1, 2, 3, 5, 7, 9, 10, 11, 12, 14, 15, 17, 19, 21, 22, 23, 26, 28, 30, 31,    \
+    37, 38, 41, 46, 47, 53, 54, 55, 60, 61, 62, 63, 76, 77, 78, 79, 80, 81,    \
+    82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,    \
+    100, 101, 102, 103, 104, 105, 106, 107
+
+void __attribute__ ((noipa))
+test_1 (int8_t *x, int8_t *y, int8_t *out)
+{
+  vnx64i v1 = *(vnx64i *) x;
+  vnx64i v2 = *(vnx64i *) y;
+  vnx64i v3 = __builtin_shufflevector (v1, v2, MASK_64);
+  *(vnx64i *) out = v3;
+}
+
+int
+main (void)
+{
+  int8_t x[64];
+  int8_t y[64];
+  int8_t out[64];
+
+  for (int i = 0; i < 64; i++)
+    {
+      x[i] = -i;
+      y[i] = i;
+    }
+
+  test_1 (x, y, out);
+
+  int mask[] = {MASK_64};
+#pragma GCC novector
+  for (int i = 0; i < 64; i++)
+    {
+      int idx = mask[i] < 64 ? mask[i] : mask[i] - 64;
+      int ref = mask[i] < 64 ? x[idx] : y[idx];
+      if (ref != out[i])
+        __builtin_abort ();
+    }
+}