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| author | Gavin Koch <gavin@cygnus.com> | 1998-05-12 08:41:11 +0000 |
|---|---|---|
| committer | Gavin Romig-Koch <gavin@gcc.gnu.org> | 1998-05-12 08:41:11 +0000 |
| commit | ec350bddd2d6250da7616b674183ccfa4e211262 (patch) | |
| tree | d14a76942bf3c4df09f4f4eba4caa69d6c8f75c0 /gcc | |
| parent | d4ba0ead26158841f25581b7fadeab674518f828 (diff) | |
| download | gcc-ec350bddd2d6250da7616b674183ccfa4e211262.zip gcc-ec350bddd2d6250da7616b674183ccfa4e211262.tar.gz gcc-ec350bddd2d6250da7616b674183ccfa4e211262.tar.bz2 | |
mips.md (dslot): Move after definition of "cpu" attribute.
* config/mips/mips.md (dslot): Move after definition of "cpu"
attribute. Handle r3900 case.
From-SVN: r19697
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 21 |
2 files changed, 17 insertions, 9 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d225d2e..ef57271 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Tue May 12 11:38:31 1998 Gavin Koch <gavin@cygnus.com> + + * config/mips/mips.md (dslot): Move after definition of "cpu" + attribute. Handle r3900 case. + Tue May 12 10:21:36 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> * system.h: Define the STRINGIFY macro here. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 37b0519..4155dd1 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -69,15 +69,6 @@ ;; # instructions (4 bytes each) (define_attr "length" "" (const_int 1)) -;; whether or not an instruction has a mandatory delay slot -(define_attr "dslot" "no,yes" - (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp") - (and (eq_attr "type" "load") - (and (eq (symbol_ref "mips_isa") (const_int 1)) - (eq (symbol_ref "mips16") (const_int 0))))) - (const_string "yes") - (const_string "no"))) - ;; Attribute describing the processor. This attribute must match exactly ;; with the processor_type enumeration in mips.h. @@ -94,6 +85,18 @@ "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000" (const (symbol_ref "mips_cpu_attr"))) +;; Does the instruction have a mandatory delay slot? +;; The 3900, is (mostly) mips1, but does not have a manditory load delay +;; slot. +(define_attr "dslot" "no,yes" + (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp") + (and (eq_attr "type" "load") + (and (eq (symbol_ref "mips_isa") (const_int 1)) + (and (eq (symbol_ref "mips16") (const_int 0)) + (eq_attr "cpu" "!r3900"))))) + (const_string "yes") + (const_string "no"))) + ;; Attribute defining whether or not we can use the branch-likely instructions (define_attr "branch_likely" "no,yes" |