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authorKazu Hirata <kazu@cs.umass.edu>2004-05-01 16:27:45 +0000
committerKazu Hirata <kazu@gcc.gnu.org>2004-05-01 16:27:45 +0000
commitea2637ebbad17a4db3173d4136dbfb2271ad77f7 (patch)
tree5439a5e349e5261fbadf3ddf9055542948216722 /gcc
parent6c3db3ab8dae232614c80abd1dd51f3b5c98aeaa (diff)
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* config/cris/cris.h: Revert my "fix comment typos" patch.
From-SVN: r81392
Diffstat (limited to 'gcc')
-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/config/cris/cris.h2
2 files changed, 5 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 71f2500..c24bd0f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2004-05-01 Kazu Hirata <kazu@cs.umass.edu>
+
+ * config/cris/cris.h: Revert my "fix comment typos" patch.
+
2004-05-01 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (TUNE_MACC_CHAINS): Fix comment.
diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h
index a4a08fe..7b028e0 100644
--- a/gcc/config/cris/cris.h
+++ b/gcc/config/cris/cris.h
@@ -337,7 +337,7 @@ extern int target_flags;
/* Whether or not to work around multiplication instruction hardware bug
when generating code for models where it may be present. From the
trouble report for Etrax 100 LX: "A multiply operation may cause
- incorrect cache behavior under some specific circumstances. The
+ incorrect cache behaviour under some specific circumstances. The
problem can occur if the instruction following the multiply instruction
causes a cache miss, and multiply operand 1 (source operand) bits
[31:27] matches the logical mapping of the mode register address